222202 ⎘
Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop; Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
FREQUENCY CORRECTION LOOP WITH DEADZONE AND HYSTERESIS
#2FAST-LOCKING PHASE-LOCKED LOOP, FREQUENCY DIVIDER, AND COMMUNICATION DEVICE
#3PHASE-LOCKED LOOP CIRCUIT AND SIGNAL PROCESSING DEVICE
#4High Gain Detector Techniques for Low Bandwidth Low Noise Phase-Locked Loops
#5High Gain Detector Techniques for High Bandwidth Low Noise Phase-Locked Loops
#6RETIMER WITH SLICER LEVEL ADJUSTMENT
#7High gain detector techniques for low bandwidth low noise phase-locked loops
#8High gain detector techniques for high bandwidth low noise phase-locked loops
#9Chirp linearity detector for radar
#10Phase-locked loop with adjustable bandwidth
#11Chirp linearity detector for radar
#12Apparatus and methods for timing offset compensation in frequency synthesizers
#13Physiological information collecting system and transceiver device thereof
#14Spread spectrum clock generation apparatus and method, and display device and touch display device
#15Phase locked loop sampler and restorer
#16Clock generator
#17Digital phase locked loop circuit adjusting digital gain to maintain loop bandwidth uniformly
#18Adaptive bandwidth systems and methods
#19Phase locked loop circuit with charge pump up-down current mismatch adjustment and static phase error reduction
#20Reception circuit
#21Clock and data recovery circuit module and phase lock method
#22Phase lock method
#23Calibration and/or adjusting gain associated with voltage-controlled oscillator
#24Phase-rotating phase locked loop and method of controlling operation thereof
#25Memory storage device having clock and data recovery circuit
#26Phase frequency detector (PFD) circuit with improved lock time
#27Adjusting voltage controlled oscillator gain
#28Capacitive load PLL with calibration loop
#29Frequency control system with dual-input bias generator to separately receive management and operational controls
#30Phase-rotating phase locked loop and method of controlling operation thereof
#31Phase frequency detector and charge pump for phase lock loop fast-locking
#32Control method for selecting frequency band and related clock data recovery device
#33Hybrid phase-locked loop architectures
#34Hybrid phase-locked loop architectures
#35Clock and data recovery circuit selectively configured to operate in one of a plurality of stages and related method thereof
#36Capactive load PLL with calibration loop
#37Transceiver using technique for improvement of phase noise and switching of phase lock loop (PLL)
#38Apparatus and methods for adjusting phase-locked loop gain
#39Clock and data recovery (CDR) architecture and phase detector thereof
#40Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency
#41Apparatus and methods for adjusting voltage controlled oscillator gain
#42System and method for reducing lock time in a phase-locked loop
#43PLL circuit
#44Semiconductor integrated circuit device
#45ADC-based mixed-mode digital phase-locked loop
#46Bandwidth control apparatus for phase lock loop and method thereof
#47Phase lock loop and control method thereof
#48Methods and apparatuses for incremental bandwidth changes responsive to frequency changes of a phase-locked loop
#49Adaptable phase lock loop transfer function for digital video interface
#50PLL Circuit
#51Low jitter large frequency tuning LC PLL for multi-speed clocking applications
#52Semiconductor integrated circuit device
#53Variable loop bandwidth phase locked loop
#54Hybrid Pll Combining Fractional-N & Integer-N Modes of Differing Bandwidths
#55Systems and methods for calibrating the loop bandwidth of a phase-locked loop (PLL)
#56Bias voltage generation circuit and clock synchronizing circuit
#57System and method for reducing lock time in a phase-locked loop
#58Oscillator signal generation with spur mitigation in a wireless communication device
#59PLL lock time reduction
#60Apparatus and method for phase lock loop gain control using unit current sources
#61Phase locked loop for stably operating in a matter that is insensitive to variation in process, voltage and temperature and method of operating the same
#62CONTINUOUS GAIN COMPENSATION AND FAST BAND SELECTION IN A MULTI-STANDARD, MULTI-FREQUENCY SYNTHESIZER
#63Semiconductor integrated circuit device
#64MEANS TO CONTROL PLL PHASE SLEW RATE
#65MEANS TO CONTROL PLL PHASE SLEW RATE
#66Apparatus and method for phase lock loop gain control using unit current sources
#67Phase-locked loop circuit
#68Dynamically adjusted phase locked loop
#69System and method for reducing transient responses in a phase lock loop with variable oscillator gain
#70Systems and Arrangements for Controlling Phase Locked Loop
#71Systems and Arrangements for Controlling a Phase Locked Loop
#72Clock and data recovery circuit
#73Phase locked loop circuit
#74Phase synchronization circuit and electronic apparatus
#75Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems
#76Continuous gain compensation and fast band selection in a multi-standard, multi-frequency synthesizer
#77Fast locking phase locked loop for synchronization with an input signal
#78Semiconductor integrated circuit having built-in PLL circuit
#79Apparatus and method for phase lock gain control using unit current sources
#80Apparatus and method for phase lock loop gain control
#81Frequency independent control
#82Method and apparatus for generating output signal
#83Phase locked loop for stably operating in a matter that is insensitive to variation in process, voltage and temperature and method of operating the same
#84Semiconductor integrated circuit having built-in PLL circuit
#85Phase lock loop indicator
#86Method for reducing phase lock time and jittering and phase lock loop using the same
#87Controlling phase locked loop in a mobile station
#88Variable loop bandwidth phase locked loop
#89Smart charge-pump circuit for phase-locked loops
#90Apparatus and method for phase lock loop gain control
#91Charge pump apparatus, system, and method
#92Partial cascode phase locked loop architecture
#93Apparatus and method for phase lock loop gain control using unit current sources
#94System and method for reducing transient response in a fractional N phase lock loop
#95Startup/yank circuit for self-biased phase-locked loops
#96PLL lock management system
#97Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems
#98Phase-locked loop with VCO tuning sensitivity compensation
#99Adaptable phase lock loop transfer function for digital video interface
#100PLL circuit and program for same
#101Method and circuit for frequency synthesis using a low drift current controlled oscillator with wide output frequency range
#102Method and system for operating a feedback system for a voltage controlled oscillator that involves correcting for offset related to the feedback system
#103Phase-locked loops
#104Oscillator, integrated circuit, and communication apparatus
#105Apparatus and method for phase lock loop gain control using unit current sources
#106Apparatus and method for phase lock loop gain control using unit current sources
#107Semiconductor integrated circuit device
#108Phase locked loop circuit with a tunable oscillator and an independent frequency converter and frequency counter
#109Phase locked loop circuit
#110Semiconductor integrated circuit having built-in PLL circuit
#111Charge pump of a phase locked loop with switchable system bandwidth and method for controlling such a charge pump
#112PLL synthesizer
#113Phase-locked loops
#114PLL circuit, radio-communication equipment and method of oscillation frequency control
#115PLL and method for providing a single/multiple adjustable frequency range
#116Charge pump circuit reducing noise and charge error and PLL circuit using the same
#117Local oscillator circuit
#118Yank detection circuit for self-biased phase locked loops
#119Apparatus and method for phase lock loop gain control using unit current sources
#120Apparatus and method for phase lock loop gain control using unit current sources
#121Semiconductor integrated circuit having built-in PLL circuit
#122Frequency and phase correction in a phase-locked loop (PLL)
#123Phase detector system with asynchronous output override
#124Apparatus and method for phase lock loop gain control using unit current sources
#125Communication semiconductor integrated circuit device and a wireless communication system
#126Method of controlling phase locked loop in mobile station, and mobile station
#127Semiconductor integrated circuit device
#128Circuit and method for faster frequency switching in a phase locked loop
#129Reducing transient response in a phase-locked loop circuit
#130Clock recovery device and method
#131Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature