ClassID:

222569

H03M5/04 - CPC Classification

Classification description:

Conversion of the form of the representation of individual digits; Conversion to or from representation by pulses the pulses having two levels

Sub-classes:
Recent Application in this class:
#1
20240152484
2024-05-09

METHODS AND APPARATUS FOR PROVIDING A SERIALIZER AND DESERIALIZER (SERDES) BLOCK FACILITATING HIGH-SPEED DATA TRANSMISSIONS FOR A FIELD-PROGRAMMABLE GATE ARRAY (FPGA)

#2
20230038814
2023-02-09

Methods and apparatus for providing a serializer and deserializer (serdes) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)

#3
20220329467
2022-10-13

Methods and systems for high bandwidth communications interface

#4
20210320672
2021-10-14

Energy efficient adaptive data encoding method and circuit

#5
20200186166
2020-06-11

Energy efficient adaptive data encoding method and circuit

#6
20190028308
2019-01-24

Methods and systems for high bandwidth communications interface

#7
20170279642
2017-09-28

Methods and systems for high bandwidth communications interface

#8
20170194012
2017-07-06

Systems and methods for compressing a digital signal

#9
20170163281
2017-06-08

Converter for converting code-modulated power with conversion code, and controller thereof

#10
20160218894
2016-07-28

Methods and systems for high bandwidth communications interface

#11
20150200737
2015-07-16

Mechanism for channel synchronization

#12
20140119427
2014-05-01

Method and apparatus for high density pulse density modulation

#13
20140028481
2014-01-30

EMI reduction with specific coding of counter signals

#14
20140016724
2014-01-16

Power and pin efficient chip-to-chip communications with common-mode rejection and SSO resilience

#15
20130279550
2013-10-24

Capacitive isolated voltage domains

#16
20130089110
2013-04-11

Mechanism for channel synchronization

#17
20120154183
2012-06-21

Multi-variable multi-wire interconnect

#18
20120075126
2012-03-29

EMI reduction with specific coding of counter signals

#19
20110302478
2011-12-08

Power and pin efficient chip-to-chip communications with common-mode rejection and SSO resilience

#20
20110156933
2011-06-30

Generating a jittered digital signal using a serializer device

#21
20110074610
2011-03-31

High speed, low power non-return-to-zero/return-to-zero output driver

#22
20090179788
2009-07-16

Analog-to-digital converter with a balanced output

#23
20090033525
2009-02-05

GAIN WEIGHTED CODE COMBINING SYSTEM AND METHOD FOR COMBINING THREE BPSK CODES

#24
20080316070
2008-12-25

Encoding of data words using three or more level levels

#25
20080191908
2008-08-14

Method and apparatus for coding information, method and apparatus for decoding coded information, method of fabricating a recording medium, the recording medium and modulated signal

#26
20080186213
2008-08-07

Mechanism for channel synchronization

#27
20080143561
2008-06-19

Operation processing apparatus, operation processing control method, and computer program

#28
20060197687
2006-09-07

Apparatus and method for encoding digital data

#29
20060187095
2006-08-24

Method and apparatus for coding information, method and apparatus for decoding coded information, method of fabricating a recording medium, the recording medium and modulated signal

#30
20060098731
2006-05-11

Digital video data transmission system and method

#31
20060098691
2006-05-11

Data carrier device, data carrier driving device, data communication system using data carrier driving device and data communication method

#32
20050122239
2005-06-09

Chip to chip interface for encoding data and clock signals

#33
20050068205
2005-03-31

Method and apparatus for coding information, method and apparatus for decoding coded information, method of fabricating a recording medium, the recording medium and modulated signal

#34
20050040975
2005-02-24

Method of generating pseudo 8B/10B code and apparatus for generating the same

#35
17318841
2022-10-18

Methods and apparatus for providing a serializer and deserializer (SERDES) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)

#36
16191936
2020-02-18

Wired-data bus transmission using signal transition coding

#37
14718407
2016-09-06

Mechanism for data generation in data processing systems