Method and system for link jitter compensation including a fast data recovery circuit

Adaptive phase recovery

Method for transporting digital media

Clock and data timing compensation for receiver

Alternating clock signal generation for delay loops

High-speed serial data transceiver and related methods

Method and apparatus for monitoring a data eye in a clock and data recovery system

Delay locked loop circuitry for clock delay adjustment

High-speed signaling systems with adaptable pre-emphasis and equalization

Phase adjustment method and circuit for DLL-based serial data link transceivers

Method and apparatus for multi-mode clock data recovery

High speed communication system with a feedback synchronization loop

Clock recovery apparatus, method, and system

Processor-controlled clock-data recovery

Mechanism to adjust a clock signal based on embedded clock information

Mechanism to aid a phase interpolator in recovering a clock signal

Phase interpolator having a phase jump

Pleisiochronous repeater system and components thereof

Interpolator systems with linearity adjustments and related methods

Clock generation using phase interpolators

High speed clock and data recovery system

Fast-lock clock-data recovery system

Clock and data recovery circuit

Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals

Quarter-rate clock recovery circuit and clock recovering method using the same

Recovery circuits and methods for the same

Circuits and methods for recovering a clock signal

Lock system and method for interpolator based receivers

Clock recovery

Phase adjustment method and circuit for DLL-based serial data link transceivers

Phase interpolator based transmission clock control

Method and apparatus for periodically retraining a serial links interface

Method of sampling data and a circuit for sampling data

Data-signal-recovery circuit, data-signal-characterizing circuit, and related integrated circuits, systems, and methods

Timing recovery of PAM signals using baud rate interpolation

Noise shaped interpolator and decimator apparatus and method

Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability

Programmable phase interpolator adjustment for ideal data eye sampling

Memory device signaling system and method with independent timing calibration for parallel signal paths

CLOCK AND DATA RECOVERY CIRCUIT

Techniques to test transmitted signal integrity

Method and apparatus for clock deskew

Semiconductor integrated circuit device and method of testing the same

Adaptive lock position circuit

Phase interpolator circuitry for reducing clock skew

Dynamic timing loop gain to compensate phase interpolation nonlinearities

Multiphase clock generation with automatic skew and amplitude control

Voltage droop monitor and voltage droop monitoring method

Shift-register-based clock phase interpolator

Bit-level mode retimer

Calibrating a phase interpolator by amplifying timing differences

Static clock calibration in physical layer device

Multi-ring cross-coupled voltage-controlled oscillator

Variable gain amplifier and sampler offset calibration without clock recovery

Preamble defect detection and mitigation

Sub-rate phase interpolator based clock data recovery architecture with phase skew correction

Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin

Efficient handling of clock offset in spread spectrum decoders

Clock-data recovery circuit with metastability detection and resolution

Mitigating interaction between adaptive equalization and timing recovery in multi-rate receiver

Data receiver circuit and method of receiving data

Synchronization for battery powered IoT networks

Clock and data recovery circuit having tunable fractional-N phase locked loop

Analog delay based fractionally spaced n-tap feed-forward equalizer for wireline and optical transmitters

Multi-signal realignment for changing sampling clock

Systems and methods for clock and data recovery

Systems and methods for clock and data recovery

Multiphase clock generation and interpolation with clock edge skew correction

Preamble defect detection and mitigation

Method of implementing a differential integrating phase interpolator

Edge rate control calibration

Method and apparatus for time tracking in OFDM wireless communication systems

SerDes with high-bandwith low-latency clock and data recovery

DFE-skewed CDR circuit

Clock and data recovery circuit and clock and data recovery method

Low-noise flexible frequency clock generation from two fixed-frequency references

Calibration of sampling phase and aperature errors in multi-phase sampling systems

Phase interpolator circuit, clock data recovery circuit including the same, and phase interpolation method

Multi-mode phase-frequency detector for clock and data recovery

Split loop timing recovery

Clock recovery circuit

Multi-channel transceiver

Phase alignment architecture for ultra high-speed data path

Data reception with feedback equalization for high and low data rates

Pre-distortion for a phase interpolator with nonlinearity

Interpolator-based clock and data recovery with reduced quantization error

Techniques for clock data recovery

Clock data recovery circuitry with programmable clock phase selection

Circuits for and methods of implementing a receiver in an integrated circuit device