PHASE INTERPOLATOR, CLOCK DATA RECOVERER, COMMUNICATION DEVICE, AND OPERATING METHOD OF PHASE INTERPOLATOR

TIME-ALIGNING DEVICE TRACE DATA

TRANSMITTER INTERPOLATING CLOCK SIGNAL, COMMUNICATION DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME

COMMUNICATION CIRCUITS INCLUDING A DIFFERENTIAL TO QUADRATURE PHASE GENERATOR

RECEIVER INCLUDING NEGATIVE COVARIANCE GENERATION FILTER AND ELECTRONIC DEVICE INCLUDING THE SAME

RECEIVER AND CLOCK AND DATA RECOVERY METHOD THEREOF

Phase Interpolation Circuit, Circuit Device, And Oscillator

PHASE INTERPOLATOR, CLOCK DATA RECOVERER, COMMUNICATION DEVICE, AND OPERATING METHOD OF PHASE INTERPOLATOR

TRANSMISSION DEVICE AND ELECTRONIC APPARATUS

Power Efficient Circuits and Methods for Phase Alignment

SELF-CLOCKED DUTY-CYCLE CORRECTED CURRENT-INTEGRATING PHASE INTERPOLATOR

MULTIPHASE CLOCK GENERATOR

FEEDFORWARD JITTER CORRECTION

METHOD AND APPARATUS FOR CLOCK AND DATA ALIGNMENT THAT REDUCES POWER CONSUMPTION

CLOCK DATA RECOVERY CIRCUIT AND APPARATUS INCLUDING THE SAME

VOLTAGE DROOP MONITOR AND VOLTAGE DROOP MONITORING METHOD

Systems for and methods of phase interpolation

Non-integer interpolation for signal sampling at asynchronous clock rates

QUADRATURE DIVIDER ERROR CORRECTION

PASSIVE PHASE INTERPOLATOR

CLOCK AND DATA RECOVERY CIRCUIT WITH SPREAD SPECTRUM CLOCKING SYNTHESIZER

RECEIVING DEVICE AND OPERATING METHOD THEREOF

Method and apparatus for clock and data alignment that reduces power consumption

REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP

Wide frequency phase interpolator

Transmission device and electronic apparatus

Method and apparatus for synchronizing frequency in remote terminals

Feedforward jitter correction

100BASE-TX TRANSCEIVER WITH TRANSMIT CLOCK IN SYNC WITH RECEIVE CLOCK FOR NOISE REDUCTION AND ASSOCIATED METHOD

Voltage droop monitor and voltage droop monitoring method

Clock data recovery with decision feedback equalization

Semiconductor integrated circuit, receiver device, and reception method

Method for measuring and correcting multi-wire skew

Clock and data recovery circuit with spread spectrum clocking synthesizer

Power efficient circuits and methods for phase alignment

Phase interpolator circuitry for a bit-level mode retimer

ELECTRONIC DEVICE FOR OUTPUTTING WIRELESS SIGNAL BASED ON CHIRP SIGNAL BY MODIFYING FREQUENCY OF FREQUENCY SYNTHESIZING CIRCUIT AND METHOD THEREOF

Clock data recovery circuit and apparatus including the same

Methods for transporting digital media

Clock and data recovery circuit and receiver

Phase interpolation based clock data recovery circuit and communication device including the same

Wide-range inductor-based delay-cell and area efficient termination switch control

Variable gain amplifier and sampler offset calibration without clock recovery

High performance phase locked loop

Clock data recovery with decision feedback equalization

Method for measuring and correcting multi-wire skew

Data-driven phase detector element for phase locked loops

Clock and data recovery circuit and receiver

Clock synchronization apparatus, optical transmitter, optical receiver, and clock synchronization method

HIGH-SPEED SIGNALING SYSTEMS WITH ADAPTABLE PRE-EMPHASIS AND EQUALIZATION

Clock generator circuit and integrated circuit including the same

Clock control device and clock control method

Clock synchronization packet exchanging method and apparatus

CLOCK RECOVERY FOR POINT-TO-MULTI-POINT COMMUNICATION SYSTEMS

Method of reading data and data-reading device

Signal processing circuit and signal processing method

Matrix phase interpolator for phase locked loop

Time lnformation Obtaining Method and Transmission Method, Terminal, and Network Device

Method for synchronizing networks

Wireless communication apparatus and coefficient update method

Variable gain amplifier and sampler offset calibration without clock recovery

CLOCK DATA RECOVERY CIRCUIT WITH IMPROVED PHASE INTERPOLATION

Memory component with pattern register circuitry to provide data patterns for calibration

Equalizer adaptation based on eye monitor measurements

System and method for providing fast-settling quadrature detection and correction

Clock data recovery device and method to alternatively adjust phases of outputted clock signals

Clock data recovery with decision feedback equalization

Variable gain amplifier and sampler offset calibration without clock recovery

Method for measuring and correcting multi-wire skew

Clock data recovery circuit

Phase interpolator

High performance phase locked loop

Receiver with clock recovery circuit and adaptive sample and equalizer timing

System and method for providing fast-settling quadrature detection and correction

Efficient handling of clock offset in spread spectrum decoders

Transmission device, reception device, communication system, signal transmission method, signal reception method, and communication method

High-speed transmitter including a multiplexer using multi-phase clocks

Clock recovery system

Fixing dead-zone in clock data recovery circuits

Asynchronous timing exchange for redundant clock synchronization

Byzantine failover of clock synchronization

Byzantine asynchronous timing exchange for multi-device clock synchronization

Multi-device asynchronous timing exchange for redundant clock synchronization

Methods for transporting digital media

Data path dynamic range optimization

Control signal transmission and reception system and control signal transmission and reception method

High speed data transfer

Matrix phase interpolator for phase locked loop

Multi-signal realignment for changing sampling clock

Method for operating a radio transmission system, and arrangement of a radio transmission system

Mixed-mode millimeter-wave transmitter

High performance phase locked loop

Jitter sensing and adaptive control of parameters of clock and data recovery circuits

Circuit for and method of receiving a signal in an integrated circuit device

Phase rotation circuit for eye scope measurements

Memory component with pattern register circuitry to provide data patterns for calibration

High-speed signaling systems with adaptable pre-emphasis and equalization

Clock data recovery with decision feedback equalization

PHASE CACHING FOR FAST DATA RECOVERY

Fast locking clock and data recovery circuit

Clock synchronization apparatus and method

Methods for transporting digital media

Jitter sensing and adaptive control of parameters of clock and data recovery circuits

Method for measuring and correcting multi-wire skew

High performance phase locked loop

Phase delay difference-based channel compensation

High-speed signaling systems with adaptable pre-emphasis and equalization

Approximated parameter adaptation

Hybrid timing recovery

Device and method for recovering clock and data

SERDES built-in sinusoidal jitter injection

Lock detector for phase lock loop

Noise generator

REAL-TIME WIRELESS POSITIONING SYSTEM AND METHOD THEREOF

Method and system for clock and data recovery (CDR)

Collaborative clock and data recovery

Phase interpolator for interpolating phase of delay clock signal and device including the same and for performing data sampling by using phase interpolated clock signal

Transmission device, reception device, communication system, signal transmission method, signal reception method, and communication method

Clock recovery circuit, semiconductor integrated circuit device and radio frequency tag

Phase adjustment circuit, control method, and measurement method

Method and apparatus for high frequency analog-to-digital conversion

Data-driven phase detector element for phase locked loops

Phase rotation circuit for eye scope measurements

Multi-level clock and data recovery circuit

Receiving device

Clock and data recovery module

Memory component with pattern register circuitry to provide data patterns for calibration

High-speed signaling systems with adaptable pre-emphasis and equalization

Communicaton unit, circuit for quadrature sampling error estimation and compensation and method therefor

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Clock data recovery with decision feedback equalization

High performance phase locked loop

Clock data recovery circuit, integrated circuit including the same, and clock data recovery method

Phased clock error handling

Compact phase interpolator

Changing the clock frequency of a computing device

Collaborative clock and data recovery

Apparatus and method for clock synchronization for inter-die synchronized data transfer

Split loop timing recovery

Burst mode clock data recovery device and method thereof

Integrated circuit and clock data recovery circuit

Methods for transporting digital media

Phase interpolator and clock and data recovery circuit

Phase locked loop (PLL) architecture

Hybrid timing for a GNSS receiver

Clock generation circuit

INTEGRATED CIRCUIT INCLUDING EQUALIZER AND METHOD FOR ADJUSTING GAIN OF EQUALIZER

Memory component with pattern register circuitry to provide data patterns for calibration

Clock and data recovery circuit and frequency detection method thereof

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Method for driving SERDES circuit

Method for performing data sampling control in an electronic device, and associated apparatus

Method and apparatus for managing estimation and calibration of non-ideality of a phase interpolator (PI)-based clock and data recovery (CDR) circuit

CDR circuit and semiconductor device

Adaptive/configurable intermediate frequency (IF) wireless receiver and bluetooth device using the same

Linearity of phase interpolators using capacitive elements

Data transmission method and data restoration method

Phase interpolator

Analog RF memory system

Noise shaped interpolator and decimator apparatus and method

Data transfer clock recovery for legacy systems

Reception circuit

Synchronization of large antenna count systems

Signaling and frame structure for massive MIMO cellular telecommunication systems

Massive MIMO architecture

Time-to-digital converter, all digital phase locked loop circuit, and method

Multilane serdes clock and data skew alignment for multi-standard support

Circuit and method for clock and data recovery

Memory component with pattern register circuitry to provide data patterns for calibration

Data signal receiver, transceiver system and method of receiving data signal

Dynamic power control for CDR

Semiconductor device

Control loop management and vector signaling code communications links

Apparatus for generating quadrature clock phases from a single-ended odd-stage ring oscillator

Multi-lane re-timer circuit and multi-lane reception system

Signal generating device

Data receivers and methods of implementing data receivers in an integrated circuit

Bimodal serial link CDR architecture

Low latency digital jitter termination for repeater circuits

Clock recovery for a data receiving unit

System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolator

Methods and systems for mobile device clock management

Method for portable device processing data based on clock extracted from data from host

Semiconductor device, portable communication terminal, IC card, and microcomputer

Reception circuit

Reception circuit and semiconductor integrated circuit device

Adaptation of crossing DFE tap weight

Phase interpolator with linear phase change

Code forwarding and clock generation for transmitter repeaters

Technique for optimizing the phase of a data signal transmitted across a communication link

Phase interpolation circuit and receiver circuit

Clock data recovery method and clock data recovery circuit

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Multilane SERDES clock and data skew alignment for multi-standard support

Digital second-order CDR circuits

Power-scalable skew compensation in source-synchronous parallel interfaces

Data transmission method and data restoration method

Apparatus and methods for quadrature clock signal generation

Method and apparatus for quantifying characteristics of a received serial data stream

Memory component with pattern register circuitry to provide data patterns for calibration

Memory component with pattern register circuitry to provide data patterns for calibration

Semiconductor device

High-speed signaling systems with adaptable pre-emphasis and equalization

NICAM decoder with output resampler

Apparatus, system, and method for timing recovery

Automatic detection and compensation of frequency offset in point-to-point communication

Phase interpolator and method of phase interpolation with reduced phase error

Data transfer clock recovery for legacy systems

Phase interpolator with independent quadrant rotation

CDR circuit, reception circuit, and electronic device

Burst Mode Clock and Data Recovery Circuit and Method

Methods and systems for adaptive receiver equalization

Apparatus, system, and method for timing recovery

Skew estimator, skew compensator and coherent receiver

Synchronized clock phase interpolator

High-speed signaling systems with adaptable pre-emphasis and equalization

Signaling with Superimposed Clock and Data Signals

Clock data recovery circuit and clock data recovery method

Systems and methods for improved timing recovery

Dynamic fault detection and repair in a data communications mechanism

Phase interpolator and semiconductor circuit device

Data judgment/phase comparison circuit

Systems and Methods for ADC Sample Based Timing Recovery

Calibration of multiple parallel data communications lines for high skew conditions

High-speed signaling systems with adaptable pre-emphasis and equalization

Phase interpolation-based clock and data recovery for differential quadrature phase shift keying

Wide band clock data recovery

NICAM decoder with output resampler

Phase interpolator based transmission clock control

High-speed signaling systems with adaptable pre-emphasis and equalization

High-speed signaling systems with adaptable pre-emphasis and equalization

Noise shaped interpolator and decimator apparatus and method

Data interface with delay locked loop for high speed digital to analog converters and analog to digital converters

Method for transporting digital media

Clock recovery

Phase adjustment apparatus and method for a memory device signaling system

Serial peripheral interface having a reduced number of connecting lines

Continuous-rate clock recovery circuit

Technique to reduce clock recovery amplitude modulation in high-speed serial transceiver

Use of data decisions for temporal placement of samplers

Spread-spectrum clock acquisition and tracking

Clock data recovery system

SYSTEMS AND METHODS FOR CLOCK CORRECTION

Method for transporting digital media

CLOCK RECOVERY CIRCUIT AND CLOCK DATA RECOVERY CIRCUIT HAVING THE SAME

Semiconductor device, portable communication terminal, IC card, and microcomputer

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Method and apparatus for multi-mode clock data recovery

Digital phase interpolation control for clock and data recovery circuit

I/O link with configurable forwarded and derived clocks

Balanced rotator conversion of serialized data

Generating multiple clock phases

Multidimensional asymmetric bang-bang control

Sign-based general zero-forcing adaptive equalizer control

ADAPTIVE CONTROL OF A DECISION FEEDBACK EQUALIZER (DFE)

Detecting residual ISI components using two data patterns

Circuits and methods for clock and data recovery

Method of processing signal data with corrected clock phase offset

Fast locking clock and data recovery

Clock and/or data recovery

Semiconductor integrated circuit device and method for clock data recovery

Clock data restoration device

Unidirectional sweep training for an interconnect

Phase interpolator for a timing signal generating circuit

Phase adjustment apparatus and method for a memory device signaling system

System and apparatus for transmitting phase information from a client to a host between read and write operations

Methods for multi-channel data detection phase locked loop frequency error combination

Methods for multi-channel data detection phase locked loop error combination

Clock data recovery (CDR) system using interpolator and timing loop module

Signaling with superimposed clock and data signals

High-speed communication system with a feedback synchronization loop

Phase select circuit with reduced hysteresis effect

Analog to digital converter clock synchronizer

Clock and data recovery circuit

Clock and data recovery circuit

Method and system for data reception with decreased bit error rate

Receiver with equalizer and method of operation

Burst mode clock and data recovery circuit and method

Methods and systems for adaptive receiver equalization

Circuit to syncrhonize the phase of a distributed clock signal with a received clock signal

Clock data recovery circuitry associated with programmable logic device circuitry

Apparatus and method of generating clock signal of semiconductor memory

Transceiver clock architecture with transmit PLL and receive slave delay lines

Digital clock recovery circuit

Sub-sampled digital programmable delay locked loop with triangular waveform preshaper

Clock and data recovery circuit

NICAM audio signal resampler

Clock and data recovery circuit and SERDES circuit

Device, system and method of frequency tracking for clock and data recovery

Transceiver with selectable data rate

Apparatus and method for retiming data using phase-interpolated clock signal

Phase-interpolator based PLL frequency synthesizer

Method of recovering digital data from a clocked serial input signal and clocked data recovery circuit

Asymmetrical IO method and system

Clock recovery

Highspeed serial transmission system and a method for reducing jitter in data transfer on such a system

Data clock recovery system and method employing delayed data clock phase shifting

Clock and data recovery circuit having wide phase margin

Circuit for measuring an eye size of data, and method of measuring the eye size of data

Data sampling circuit and semiconductor integrated circuit