242022 ⎘
Semiconductor device manufacturing: process Germanium or silicon or Ge-Si on III-V
Method for improving transistor performance through reducing the salicide interface resistance
#2Method for improving transistor performance through reducing the salicide interface resistance
#3Silicon germanium source/drain regions
#4Method for improving transistor performance through reducing the salicide interface resistance
#5Reduced resistance SiGe FinFET devices and method of forming same
#6Method of manufacturing semiconductor device
#7Strained silicon nFET and silicon germanium pFET on same wafer
#8Strained silicon nFET and silicon germanium pFET on same wafer
#9Method of manufacturing semiconductor lasers
#10Method for improving transistor performance through reducing the salicide interface resistance
#11In-situ doping of arsenic for source and drain epitaxy
#12Silicon/germanium oxide particle inks and processes for forming solar cell components and for forming optical components
#13Semiconductor memory cell, device, and method for manufacturing the same
#14METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR
#15Damascene process for use in fabricating semiconductor structures having micro/nano gaps
#16Manufacture of semiconductor device with stress structure
#17Manufacture of semiconductor device with stress structure
#18Silicon/germanium oxide particle inks and processes for forming solar cell components and for forming optical components
#19STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMING
#20Silicon/germanium oxide particle inks, inkjet printing and processes for doping semiconductor substrates
#21Method for improving transistor performance through reducing the salicide interface resistance
#22Methods and Compositions for Preparing Ge/Si Semiconductor Substrates
#23Reconditioned substrates for fabricating compound material wafers
#24Field-effect transistor and method for fabricating the same
#25Field effect transistor with a heterostructure
#26Semiconductor device manufacturing method
#27Method for improving transistor performance through reducing the salicide interface resistance
#28Method for manufacturing an III-V engineered substrate and the III-V engineered substrate thereof
#29Method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side
#30Light emitting apparatus
#31High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof
#32Methods for making and using halosilylgermanes
#33FIN field effect transistor
#34Transistor having a high-k metal gate stack and a compressively stressed channel
#35Manufacture of semiconductor device with stress structure
#36Method of fabricating a MEMS/NEMS electromechanical component
#37Process for deposition of semiconductor films
#38Multilayer structure and fabrication thereof
#39Tensile strained NMOS transistor using group III-N source/drain regions
#40Semiconductor device including non-stoichiometric silicon carbide layer and method of fabrication thereof
#41Monolithically integrated photodetectors
#42Semiconductor surface treatment for epitaxial growth
#43CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode
#44Methods for fabricating compound material wafers
#45Strain-direct-on-insulator (SDOI) substrate and method of forming
#46Deformation moderation method
#47Field effect transistor with a heterostructure
#48Tensile strained GE for electronic and optoelectronic applications
#49Transistor and in-situ fabrication process
#50Method of forming nanowire and method of manufacturing semiconductor device comprising the nanowire
#51Process for depositing layers containing silicon and germanium
#52Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
#53Method of fabrication of metal oxide semiconductor field effect transistor
#54FIN field effect transistor
#55Method to improve performance of secondary active components in an esige CMOS technology
#56Defect reduction by oxidation of silicon
#57Shallow trench isolation process and structure with minimized strained silicon consumption
#58Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
#59Method of fabricating semiconductor optical device
#60Multilayer structure and fabrication thereof
#61SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
#62Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
#63Silicon/germanium oxide particle inks, inkjet printing and processes for doping semiconductor substrates
#64Silicon/germanium particle inks, doped particles, printing and processes for semiconductor applications
#65Silicide formation on SiGe
#66Structure of strained silicon on insulator and method of manufacturing the same
#67Integrated circuit structures having a boron- and carbon-doped etch-stop and methods, devices and systems related thereto
#68Structure of strained silicon on insulator and method of manufacturing the same
#69Thin films and methods of making them
#70Method for improving transistor performance through reducing the salicide interface resistance
#71Semiconductor devices having a field effect transistor and methods of fabricating the same
#72Method of forming an integrated circuit having a device wafer with a diffused doped backside layer
#73Deposition over mixed substrates using trisilane
#74STRUCTURE OF STRAINED SILICON ON INSULATOR AND METHOD OF MANUFACTURING THE SAME
#75Method for fabricating a component having an electrical contact region
#76Metal oxide semiconductor field effect transistor with strained source/drain extension layer
#77Low-temperature metal-induced crystallization of silicon-germanium films
#78Method of manufacturing a strained semiconductor layer, method of manufacturing a semiconductor device and semiconductor substrate suitable for use in such a method including having a thin delta profile layer of germanium close to the bottom of the strained layer
#79Selective epitaxy process with alternating gas supply
#80Method of forming device having a raised extension region
#81Tensile strained NMOS transistor using group III-N source/drain regions
#82Method of fabricating a low, dark-current germanium-on-silicon pin photo detector
#83Epitaxy layer and method of forming the same
#84Fabrication method of a semiconductor device
#85Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer
#86Monolithically integrated silicon and III-V electronics
#87Monolithically integrated semiconductor materials and devices
#88Monolithically integrated light emitting devices
#89Process for deposition of semiconductor films
#90Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
#91Method for making a semiconductor structure using silicon germanium
#92High performance microwave switching devices and circuits
#93Field-effect transistor and method for fabricating the same
#94Semiconductor device and method of manufacturing the same
#95Field effect transistor with a heterostructure and associated production method
#96WAFER GETTERING USING RELAXED SILICON GERMANIUM EPITAXIAL PROXIMITY LAYERS
#97Transistor with shallow germanium implantation region in channel
#98Surface-emitting semiconductor laser comprising a structured waveguide
#99Structure for and method of fabricating a high-mobility field-effect transistor
#100Implantation-less approach to fabricating strained semiconductor on isolation wafers
#101Transistor with shallow germanium implantation region in channel
#102Rugged metal electrodes for metal-insulator-metal capacitors
#103Selective epitaxy process with alternating gas supply
#104Bonded semiconductor substrate
#105Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
#106Thin germanium oxynitride gate dielectric for germanium-based devices
#107Method of forming a semiconductor device and an optical device and structure thereof
#108Method of obtaining release-standing micro structures and devices by selective etch removal of protective and sacrificial layer using the same
#109Producing stress-relaxed crystalline layer on a substrate
#110Semiconductor layer and forming method thereof, and semiconductor device and manufacturing method thereof technical field
#111Treatment of a removed layer of silicon-germanium
#112Structure and method of forming a notched gate field effect transistor
#113Semiconductor integrated circuit and fabrication process thereof
#114Tensile strained substrate
#115Method of estimating substrate temperature
#116Structure of strained silicon on insulator and method of manufacturing the same
#117Microelectronic programmable device and methods of forming and programming the same
#118Selective epitaxy process with alternating gas supply
#119Method for forming low defect density alloy graded layers and structure containing such layers
#120Recycling the reconditioned substrates for fabricating compound material wafers
#121Method for manufacturing a semiconductor device with reduced floating body effect
#122Semiconductor device and process for manufacturing the same
#123Method to form relaxed SiGe layer with high Ge content using co-implantation of silicon with boron or helium and hydrogen
#124Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
#125Methods of fabricating strained-channel FET having a dopant supply region
#126Integrated circuit having a device wafer with a diffused doped backside layer
#127Methods of forming semiconductor circuitry
#128III-V and II-VI compounds as template materials for growing germanium containing film on silicon
#129Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby
#130Method for improving transistor performance through reducing the salicide interface resistance
#131Epitaxy layer and method of forming the same
#132Thin films and methods of making them
#133Damascene process for use in fabricating semiconductor structures having micro/nano gaps
#134Method for making a semiconductor structure using silicon germanium
#135Formation of lattice-tuning semiconductor substrates
#136High speed lateral heterojunction MISFETS realized by 2-dimensional bandgap engineering and methods thereof
#137Semiconductor devices having a field effect transistor and methods of fabricating the same
#138Methods of making semiconductor-on-insulator thin film transistor constructions
#139Methods of fabricating dual layer semiconductor devices
#140Process for deposition of semiconductor films
#141Transistor with shallow germanium implantation region in channel
#142Method for depositing a group III-nitride material on a silicon substrate and device therefor
#143Methods and structures for metal interconnections in integrated circuits
#144Rare earth-oxides, rare earth-nitrides, rare earth-phosphides and ternary alloys with silicon
#145Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
#146Structure and method of forming a notched gate field effect transistor
#147Shallow trench isolation process and structure with minimized strained silicon consumption
#148Method of preventing surface roughening during hydrogen prebake of SiGe substrates
#149Strained silicon on a SiGe on SOI substrate
#150Strained dislocation-free channels for CMOS and method of manufacture
#151Cobalt silicidation process for substrates with a silicon—germanium layer
#152Method for improving transistor performance through reducing the salicide interface resistance
#153Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion
#154Method of manufacturing a strained silicon on a SiGe on SOI substrate
#155Method of producing semiconductor crystal
#156Method for fabricating a component having an electrical contact region, and component having an electrical contact region
#157Semiconductor device
#158Wafer bonded virtual substrate and method for forming the same
#159Method of manufacturing strained dislocation-free channels for CMOS
#160Structure for and method of fabricating a high-mobility field-effect transistor
#161Thin germanium oxynitride gate dielectric for germanium-based devices
#162Indirect bonding with disappearance of bonding layer
#163Semiconductor layer formation
#164Method of manufacturing SOI template layer
#165Template layer formation
#166Process for deposition of semiconductor films
#167Capping layer for crystallizing germanium, and substrate having thin crystallized germanium layer
#168Deposition over mixed substrates
#169Formation of finFET using a sidewall epitaxial layer
#170Method of forming GE photodetectors
#171Semiconductor device and method of manufacturing the same
#172Process for producing semiconductor article using graded epitaxial growth
#173Field-effect type semiconductor device for power amplifier
#174Defect reduction by oxidation of silicon