242027 ⎘
Semiconductor device manufacturing: process Lattice strain control or utilization
Method of forming semiconductor device
#2Asymmetric cyclic desposition etch epitaxy
#3Semiconductor memory cell, device, and method for manufacturing the same
#4METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR
#5STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS
#6STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS
#7Technique for the growth of planar semi-polar gallium nitride
#8Vertical group III-V nanowires on si, heterostructures, flexible arrays and fabrication
#9Methods of manufacturing semiconductor devices including forming (111) facets in silicon capping layers on source/drain regions
#10MOS devices with partial stressor channel
#11Structure with isotropic silicon recess profile in nanoscale dimensions
#12Field-effect transistor and method for fabricating the same
#13Semiconductor device manufacturing method
#14Method for manufacturing an III-V engineered substrate and the III-V engineered substrate thereof
#15Process for transferring a layer of strained semiconductor material
#16Semiconductor device and method of fabricating the same
#17Strain balanced light emitting devices
#18Technique for the growth of planar semi-polar gallium nitride
#19High performance stress-enhance MOSFET and method of manufacture
#20Memory device and method for manufacturing the same
#21Memory device and method for manufacturing the same
#22Tensile strained NMOS transistor using group III-N source/drain regions
#23Method of producing a tensioned layer on a substrate
#24Relaxation of a strained layer using a molten layer
#25MOS devices with partial stressor channel
#26Tensile strained GE for electronic and optoelectronic applications
#27Method for manufacturing semiconductor substrate, display panel, and display device
#28Method of fabrication of metal oxide semiconductor field effect transistor
#29Methods of fabrication of channel-stressed semiconductor devices
#30Flexible and elastic dielectric integrated circuit
#31Process for transferring a layer of strained semiconductor material
#32Strain enhanced semiconductor devices and methods for their fabrication
#33PMD liner nitride films and fabrication methods for improved NMOS performance
#34HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS
#35Structure and methods for stress concentrating spacer
#36Method for improved fabrication of a semiconductor using a stress proximity technique process
#37SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
#38Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate
#39Uniaxial strain relaxation of biaxial-strained thin films using ion implantation
#40Process for transferring a layer of strained semiconductor material
#41Etching method and structure using a hard mask for strained silicon MOS transistors
#42Device having enhanced stress state and related methods
#43Semiconductor device and fabrication method thereof
#44Methods for selective placement of dislocation arrays
#45MOS devices with partial stressor channel
#46Method for patterning contact etch stop layers by using a planarization process
#47Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel
#48Strained fully depleted silicon on insulator semiconductor device
#49Semiconductor device and method for manufacturing the same
#50High performance CMOS device structures and method of manufacture
#51FABRICATION METHODS FOR COMPRESSIVE STRAINED-SILICON AND TRANSISTORS USING THE SAME
#52Method and structure for forming self-aligned, dual stress liner for CMOS devices
#53Multiple conduction state devices having differently stressed liners
#54Hetero-integrated strained silicon n- and p-MOSFETs
#55High performance stress-enhance MOSFET and method of manufacture
#56High performance stress-enhance MOSFET and method of manufacture
#57Metal oxide semiconductor field effect transistor with strained source/drain extension layer
#58Semiconductor device made by multiple anneal of stress inducing layer
#59Dual stressed SOI substrates
#60STRUCTURE AND METHOD FOR MANUFACTURING PLANAR STRAINED Si/SiGe SUBSTRATE WITH MULTIPLE ORIENTATIONS AND DIFFERENT STRESS LEVELS
#61Tensile strained NMOS transistor using group III-N source/drain regions
#62Technique for the growth of planar semi-polar gallium nitride
#63Method of fabricating strained-silicon transistors
#64Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer
#65Field-effect transistor and method for fabricating the same
#66Formation of strained Si channel and SiGesource/drain structures using laser annealing
#67Methods for fabricating a stressed MOS device
#68Methods of fabricating semiconductor devices having strained dual channel layers
#69Self-aligned dual stressed layers for NFET and PFET
#70Gate material for semiconductor device fabrication
#71Structure for and method of fabricating a high-mobility field-effect transistor
#72METHOD OF FABRICATING SEMICONDUCTOR DEVICES AND METHOD OF ADJUSTING LATTICE DISTANCE IN DEVICE CHANNEL
#73Method for producing a tensioned layer on a substrate, and a layer structure
#74Enhancing strained device performance by use of multi narrow section layout
#75Technique for the growth of planar semi-polar gallium nitride
#76Method and structure for forming self-aligned, dual stress liner for CMOS devices
#77Relaxation of a strained layer using a molten layer
#78Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
#79Semiconductor layer and forming method thereof, and semiconductor device and manufacturing method thereof technical field
#80Strained channel CMOS device with fully silicided gate electrode
#81Memory device and method for manufacturing the same
#82Semiconductor device and method for manufacturing the same
#83Semiconductor device comprising a crystalline layer containing silicon/germanium, and comprising a silicon Enriched floating charge trapping media over the crystalline layer
#84Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain
#85Manufacturing method for a MOS transistor comprising layered relaxed and strained SiGe layers as a channel region
#86Device having enhanced stress state and related methods
#87Dual stressed SOI substrates
#88Method for forming low defect density alloy graded layers and structure containing such layers
#89Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor
#90Method for forming integrated advanced semiconductor device using sacrificial stress layer
#91Memory with strained semiconductor by wafer bonding with misorientation
#92Hetero-integrated strained silicon n- and p-MOSFETs
#93Semiconductor device and process for manufacturing the same
#94Gate material for semiconductor device fabrication
#95Control of strain in device layers by prevention of relaxation
#96Method of making a semiconductor device having a strained semiconductor layer
#97Technique for transferring strain into a semiconductor region
#98Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
#99Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
#100Technique for controlling mechanical stress in a channel region by spacer removal
#101Fabrication methods for compressive strained-silicon and transistors using the same
#102Process for transferring a layer of strained semiconductor material
#103PMD liner nitride films and fabrication methods for improved NMOS performance
#104Semiconductor device and method of manufacturing same
#105Enhancing strained device performance by use of multi narrow section layout
#106Fabrication of nonpolar indium gallium nitride thin films, heterostructures and devices by metalorganic chemical vapor deposition
#107Strained silicon-channel MOSFET using a damascene gate process
#108Strained-channel semiconductor structure and method of fabricating the same
#109Method of making an integrated circuit
#110Lithography device for semiconductor circuit pattern generation
#111Flexible and elastic dielectric integrated circuit
#112Membrane 3D IC fabrication
#113Strained channel transistor formation
#114Structure for and method of fabricating a high-mobility field-effect transistor
#115Stress-controlled dielectric integrated circuit
#116Strained silicon-channel MOSFET using a damascene gate process
#117Field effect transistor having increased carrier mobility
#118Strained semiconductor by wafer bonding with misorientation