242036 ⎘
Semiconductor device manufacturing: process; Masking Subphotolithographic processing
SEMICONDUCTOR PATTERNING AND RESULTING STRUCTURES
#2METHOD FOR FORMING PATTERNED MASK LAYER
#3Semiconductor Patterning and Resulting Structures
#4Method for forming patterned mask layer
#5Semiconductor patterning and resulting structures
#6Method for forming patterned mask layer
#7Semiconductor patterning and resulting structures
#8Alternating hardmasks for tight-pitch line formation
#9Alternating hardmasks for tight-pitch line formation
#10Alternating hardmasks for tight-pitch line formation
#11Method for modifying spacer profile
#12Methods for manufacturing a spacer with desired profile in an advanced patterning process
#13Self-aligned quadruple patterning process
#14Methods of forming semiconductor device structures including metal oxide structures
#15Integrated circuit fabrication
#16Multi-patterning method and device formed by the method
#17Gate electrode with a shrink spacer
#18Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
#19Integrated circuit fabrication
#20Grapho-epitaxy DSA process with dimension control of template pattern
#21Pattern forming method
#22Methods for fabricating integrated circuits with improved semiconductor fin structures
#23Methods for fabricating electrically-isolated finFET semiconductor devices
#24Multi-patterning method and device formed by the method
#25Methods of forming a pattern on a substrate
#26Semiconductor device structures including metal oxide structures
#27Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
#28Primer and pattern forming method for layer including block copolymer
#29High temperature thermal annealing process
#30Thermal annealing process
#31Integrated circuit fabrication
#32Polymeric materials in self-assembled arrays and semiconductor structures comprising polymeric materials
#33Methods using block co-polymer self-assembly for sub-lithographic patterning
#34Semiconductor device and manufacturing method of semiconductor device
#35Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etch
#36Critical dimension reduction and roughness control
#37Method of manufacturing semiconductor device and system for manufacturing semiconductor device
#38Patterning method for high density pillar structures
#39Integrated circuit structure having arrays of small, closely spaced features
#40Integrated circuit fabrication
#41Processes and apparatus having a semiconductor fin
#42Integrated circuit pattern and method
#43Method for fabricating large-area nanoscale pattern
#44MULTI-EXPOSURE LITHOGRAPHY EMPLOYING DIFFERENTIALLY SENSITIVE PHOTORESIST LAYERS
#45Template-registered diblock copolymer mask for MRAM device formation
#46Polymer materials for formation of registered arrays of cylindrical pores
#47Graphoepitaxial self-assembly of arrays of downward facing half-cylinders
#48Semiconductor structures including polymer material permeated with metal oxide
#49Double patterning with inline critical dimension slimming
#50Sidewall image transfer pitch doubling and inline critical dimension slimming
#51Methods of forming a non-volatile resistive oxide memory array
#52Method of forming pattern, reticle, and computer readable medium for storing program for forming pattern
#53Registered structure formation via the application of directed thermal energy to diblock copolymer films
#54STRUCTURES WITH INCREASED PHOTO-ALIGNMENT MARGINS
#55Method for manufacturing porous structure and method for forming pattern
#56Method for manufacturing porous structure and method for forming pattern
#57Method for manufacturing porous structure and method for forming pattern
#58Patterning method for high density pillar structures
#59Methods of forming patterned photoresist layers over semiconductor substrates
#60Methods using block co-polymer self-assembly for sub-lithographic patterning
#61Nonvolative memory device using semiconductor nanocrystals and method of forming same
#62Patterning method for high density pillar structures
#63Method of fabricating semiconductor device
#64Nonvolatile memory device using semiconductor nanocrystals and method of forming same
#65Processes and apparatus having a semiconductor fin
#66Device and methodology for reducing effective dielectric constant in semiconductor devices
#67Template-registered diblock copolymer mask for MRAM device formation
#68Embedded phase-change memory and method of fabricating the same
#69Phase change memory cell and devices containing same
#70Pitch multiplication using self-assembling materials
#71Integrated circuit fabrication
#72Method of forming sub-lithographic features using directed self-assembly of polymers
#73Method of manufacturing flat panel display
#74Method of forming multi-high-density memory devices and architectures
#75Process for increasing feature density during the manufacture of a semiconductor device
#76Method of pitch halving
#77Fin and finFET formation by angled ion implantation
#78Method for integrated circuit fabrication using pitch multiplication
#79Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features
#80Method for producing semiconductor device
#81Method of fabricating phase change memory cell
#82Critical dimension reduction and roughness control
#83Method for selectively permeating a self-assembled block copolymer, method for forming metal oxide structures, method for forming a metal oxide pattern, and method for patterning a semiconductor structure
#84Manufacturing method of semiconductor device
#85Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
#86Method for improving semiconductor surfaces
#87Methods of forming a non-volatile resistive oxide memory array
#88Nonvolatile memory device using semiconductor nanocrystals and method forming same
#89Multi-exposure lithography employing differentially sensitive photoresist layers
#90Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
#91Graphoepitaxial self-assembly of arrays of downward facing half-cylinders
#92Multi-layer method for formation of registered arrays of cylindrical pores in polymer films
#93Method for forming pattern of a semiconductor device
#94Method of making diamond nanopillars
#95Patterning of submicron pillars in a memory array
#96Method of fabricating semiconductor device
#97METHOD OF TRIMMING A HARD MASK LAYER, METHOD FOR FABRICATING A GATE IN A MOS TRANSISTOR, AND A STACK FOR FABRICATING A GATE IN A MOS TRANSISTOR
#98THIN FILM TRANSISTOR ARRAY PANEL FOR A LIQUID CRYSTAL DISPLAY AND A METHOD FOR MANUFACTURING THE SAME
#99Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques
#100Method for manufacturing porous structure and method for forming pattern
#101Small electrode for phase change memories
#102Method for producing a nanoporous substrate
#103Method of manufacturing flat panel display
#104Inverse self-aligned spacer lithography
#105Pitch multiplication using self-assembling materials
#106Frequency tripling using spacer mask having interposed regions
#107Methods for generating sublithographic structures
#108Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features
#109Methods for forming arrays of small, closely spaced features
#110Reducing effective dielectric constant in semiconductor devices
#111Method for adjusting feature size and position
#112Intermediate semiconductor device structures
#113Integrated circuit fabrication
#114Registered structure formation via the application of directed thermal energy to diblock copolymer films
#115Field effect transistor device including an array of channel elements
#116Method of fabricating a semiconductor device comprising high and low density patterned contacts
#117Methods of manufacturing semiconductor device
#118Methods using block copolymer self-assembly for sub-lithographic patterning
#119Sub-lithographic interconnect patterning using self-assembling polymers
#120Methods for removing photoresist from semiconductor structures having high-k dielectric material layers
#121Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a stack for fabricating a gate in a MOS transistor
#122System and method for filling vias
#123Device patterned with sub-lithographic features with variable widths
#124Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
#125Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
#126Processes and apparatus having a semiconductor fin
#127Method for forming fine patterns of a semiconductor device using double patterning
#128Method of forming pad patterns using self-align double patterning method, pad pattern layout formed using the same, and method of forming contact holes using self-align double patterning method
#129Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
#130Small electrode for phase change memories
#131Device and methodology for reducing effective dielectric constant in semiconductor devices
#132Device and methodology for reducing effective dielectric constant in semiconductor devices
#133Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same
#134Multi-bit high-density memory device and architecture and method of fabricating multi-bit high-density memory devices
#135Etching method, plasma processing system and storage medium
#136Forming phase change memory arrays
#137MEMORY CELL WITH REDUCED SIZE AND STANDBY CURRENT
#138Patterning sub-lithographic features with variable widths
#139Method for producing an optoelectronic component
#140Semiconductor device and method of manufacture thereof
#141Semiconductor device and method of manufacture thereof
#142Guard ring for improved matching
#143Method of edge bevel rinse
#144Embedded phase-change memory and method of fabricating the same
#145Method for integrated circuit fabrication using pitch multiplication
#146Method for realizing a multispacer structure, use of said structure as a mold and circuital architectures obtained from said mold
#147Process for increasing feature density during the manufacture of a semiconductor device
#148Method of forming micro patterns in semiconductor devices
#149Method for forming recesses
#150Method for forming recesses
#151Method of fabricating a semiconductor device
#152Method for manufacturing a narrow structure on an integrated circuit
#153Method and apparatus for adjusting feature size and position
#154Three-dimensional structure composed of silicon fine wires, method for producing the same, and device including the same
#155Critical dimension reduction and roughness control
#156Methods for increasing photo-alignment margins
#157Structures with increased photo-alignment margins
#158Methods for increasing photo-alignment margins
#159Methods for forming arrays of small, closely spaced features
#160Method for integrated circuit fabrication using pitch multiplication
#161Method for integrated circuit fabrication using pitch multiplication
#162Methods of forming patterned photoresist layers over semiconductor substrates
#163Field effect transistor device including an array of channel elements and methods for forming
#164Method for manufacturing porous structure and method for forming pattern
#165Methods for increasing photo alignment margins
#166Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same
#167Integrated circuit fabrication
#168Integrated circuit fabrication
#169Stabilized photoresist structure for etching process
#170Method for patterning submicron pillars
#171Method of forming a nonvolatile memory device using semiconductor nanoparticles
#172Nanocircuit and self-correcting etching method for fabricating same
#173Memory device including resistance change layer as storage node and method(s) for making the same
#174Guard ring for improved matching
#175Forming phase change memory arrays
#176Method for integrated circuit fabrication using pitch multiplication
#177Methods for increasing photo alignment margins
#178Method of forming narrowly spaced flash memory contact openings and lithography masks
#179Method of reducing pattern pitch in integrated circuits
#180Exposure apparatus
#181Method of pitch dimension shrinkage
#182Integrated circuit having pairs of parallel complementary FinFETs
#183Optoelectronic component having a plurality of current expansion layers and method for producing it
#184Three-dimensional structural body composed of silicon fine wire, its manufacturing method, and device using same
#185High surface area capacitor structures and precursors
#186Method for making a semiconductor device using treated photoresist as an implant mask
#187Method of making a semiconductor device using treated photoresist
#188Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
#189Device and methodology for reducing effective dielectric constant in semiconductor devices
#190Liquid-filled balloons for immersion lithography
#191Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
#192Nanocircuit and self-correcting etching method for fabricating same
#193Methods of forming patterned photoresist layers over semiconductor substrates
#194Method for forming dual damascenes
#195Method of fabricating a conductive path in a semiconductor device
#196Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same
#197Integrated circuit having pairs of parallel complementary FinFETs