Kameswar Subramaniam

SYSTEM, APPARATUS AND METHODS FOR PERFORMANT READ AND WRITE OF PROCESSOR STATE INFORMATION RESPONSIVE TO LIST INSTRUCTIONS

CONCURRENT DECODE OF COMPLEX INSTRUCTIONS HAVING VARYING NUMBERS OF DECODED INSTRUCTIONS

REGION-AWARE MEMORY BANDWIDTH ALLOCATION CONTROL

INSTRUCTIONS FOR WRITE AND/OR READ OF CONTROL AND/OR STATUS REGISTERS

SUPPORT FOR A 32-BIT IMMEDIATE AS INDICATED BY AN INSTRUCTION PREFIX

PREFETCHER WITH LOW-LEVEL SOFTWARE CONFIGURABILITY

ISSUE, EXECUTION, AND BACKEND DRIVEN FRONTEND TRANSLATION CONTROL FOR PERFORMANT AND SECURE DATA-SPACE GUIDED MICRO-SEQUENCING

Loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing

System, Apparatus And Methods For Minimum Serialization In Response To Non-Serializing Register Write Instruction

SYSTEM, APPARATUS AND METHODS FOR PERFORMANT READ AND WRITE OF PROCESSOR STATE INFORMATION RESPONSIVE TO LIST INSTRUCTIONS

METHODS, SYSTEMS, AND APPARATUSES TO OPTIMIZE CROSS-LANE PACKED DATA INSTRUCTION IMPLEMENTATION ON A PARTIAL WIDTH PROCESSOR WITH A MINIMAL NUMBER OF MICRO-OPERATIONS

PROCESSOR, METHOD, AND SYSTEM FOR REDUCING LATENCY IN ACCESSING REMOTE REGISTERS

System, apparatus and method for providing hardware feedback information in a processor

Providing autonomous self-testing of a processor

Optimized mode transitions through predicting target state

Context control and parameter passing within microcode based instruction routines

Enhanced microcode address stack pointer manipulation

Programmable logic array and read-only memory area reduction using context-sensitive logic for data space manipulation

Execute at commit state update instructions, apparatus, methods, and systems

Aliased Parameter Passing Between Microcode Callers and Microcode Subroutines

Saving Values Corresponding to Parameters Passed Between Microcode Callers and Microcode Subroutines from Microcode Alias Locations to a Destination Storage Location