Haifa
Israel
31
2025-10-02
The entities that hold a legal rights for patent applications filed by inventor Mandelblat Julius:
Julius Mandelblat from Haifa, IL has applied for patents for these inventions. The list has both pending applications and granted patents:
Apparatus and Method for Performance and Energy Efficient Compute
#2 | 2025-10-02COHERENT CACHE FABRIC WITH REDUCED POWER MODE
#3 | 2025-10-02APPARATUS AND METHOD INCLUDING SCHEDULING SUPPORT CIRCUITRY FOR SCHEDULING TASKS ON AN EFFICIENCY CLUSTER FOR IMPROVED PERFORMANCE
#4 | 2025-07-03Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement
#5 | 2024-07-04DYNAMIC ALLOCATION SCHEMES IN MEMORY SIDE CACHE FOR BANDWIDTH AND PERFORMANCE OPTIMIZATION
#6 | 2024-06-20INTEGRATED CIRCUIT CHIP TO SELECTIVELY PROVIDE TAG ARRAY FUNCTIONALITY OR CACHE ARRAY FUNCTIONALITY
#7 | 2023-01-19DEVICE, METHOD AND SYSTEM TO PROVIDE THREAD SCHEDULING HINTS TO A SOFTWARE PROCESS
#8 | 2022-01-13METHODS AND APPARATUS TO INCREASE BOOT PERFORMANCE
#9 | 2021-12-02Systems, apparatuses, and methods for resource bandwidth enforcement
#10 | 2021-07-01Apparatus and method for adaptively scheduling work on heterogeneous processing resources
#11 | 2021-07-01Performance monitoring in heterogeneous systems
#12 | 2019-04-04CACHE BEHAVIOR FOR SECURE MEMORY REPARTITIONING SYSTEMS
#13 | 2019-02-07Architecture for dynamic transformation of memory configuration
#14 | 2018-12-27System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms
#15 | 2018-07-05Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures
#16 | 2018-04-05Systems and methods for enhancing BIOS performance by alleviating code-size limitations
#17 | 2017-07-06Cache allocation with code and data prioritization
#18 | 2016-10-13Cache allocation with code and data prioritization
#19 | 2016-09-29Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement
#20 | 2015-07-02ADAPTIVE ADMISSION CONTROL FOR ON DIE INTERCONNECT
#21 | 2015-01-01Hybrid exclusive multi-level memory architecture with memory management
#22 | 2014-12-25Restricting clock signal delivery in a processor
#23 | 2014-10-02Apparatus and method for implement a multi-level memory hierarchy
#24 | 2011-12-29G-ODLAT on-die logic analyzer trigger with parallel vector finite state machine
#25 | 2010-06-24Posting weakly ordered transactions
#26 | 2009-12-03Reducing back invalidation transactions from a snoop filter
#27 | 2007-07-19Method and apparatus of reporting memory bit correction
#28 | 2007-07-05Device, system and method of managing a resource request
#29 | 2007-06-28Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach
#30 | 2007-06-28Device, system and method of multi-state cache coherence scheme
#31 | 2007-02-22Dynamic memory sizing for power reduction
1017464 ⎘