Austin, Texas
United States
83
2024-04-30
The entities that hold a legal rights for patent applications filed by inventor Qi Jieming:
Jieming Qi from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Calibrating a quadrature receive serial interface
#2 | 2024-04-11Communication systems for power supply noise reduction
#3 | 2024-04-11Communication systems for power supply noise reduction
#4 | 2024-03-21Quadrature circuit interconnect architecture with clock forwarding
#5 | 2023-08-24Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output
#6 | 2019-06-13Single-lock delay locked loop with cycle counter and method therefor
#7 | 2018-12-06Single-lock delay locked loop with cycle counter and method therefor
#8 | 2018-08-21Single-lock delay locked loop with cycle counter and method therefore
#9 | 2015-01-15Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations
#10 | 2012-01-05Variable gain amplifier with reduced power consumption
#11 | 2011-10-06Controlling bandwidth reservations method and apparatus
#12 | 2011-05-26Structure for a duty cycle correction circuit
#13 | 2011-05-26Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction
#14 | 2010-07-01High speed clock signal duty cycle adjustment
#15 | 2009-12-31Clock duty cycle measurement with charge pump without using reference clock calibration
#16 | 2009-12-31Method and Apparatus for On-Chip Testing of High Speed Frequency Dividers
#17 | 2009-11-19Phase locked loop with temperature and process compensation
#18 | 2009-07-16Structure for a programmable interpolative voltage controlled oscillator with adjustable range
#19 | 2009-06-11Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction
#20 | 2009-05-28Structure for a duty cycle measurement circuit
#21 | 2009-05-21Structure for a circuit obtaining desired phase locked loop duty cycle without pre-scaler
#22 | 2009-05-21Apparatus and Method for Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler
#23 | 2009-05-21Duty cycle measurement for various signals throughout an integrated circuit device
#24 | 2009-05-14Structure for an absolute duty cycle measurement circuit
#25 | 2009-05-14Absolute duty cycle measurement
#26 | 2009-04-30Design structure for a duty cycle measurement apparatus that operates in a calibration mode and a test mode
#27 | 2009-04-30Structure for managing voltage swings across field effect transistors
#28 | 2009-04-30Structure for precision integrated phase lock loop circuit loop filter
#29 | 2009-04-30Method and system for managing voltage swings across field effect transistors
#30 | 2009-04-30Precision integrated phase lock loop circuit loop filter
#31 | 2009-03-12Programmable Interpolative Voltage Controlled Oscillator with Adjustable Range
#32 | 2009-01-22Adjusting voltage for a phase locked loop based on temperature
#33 | 2009-01-22Structure for a phase locked loop with adjustable voltage based on temperature
#34 | 2009-01-01Design structure for a phase locked loop with stabilized dynamic response
#35 | 2009-01-01Phase Locked Loop with Stabilized Dynamic Response
#36 | 2008-12-18Systems and methods for level shifting using AC coupling
#37 | 2008-10-09Duty cycle correction circuit whose operation is largely independent of operating voltage and process
#38 | 2008-09-18Structure for a duty cycle correction circuit
#39 | 2008-09-11Structure for interleaved voltage controlled oscillator
#40 | 2008-08-14Interleaved voltage controlled oscillator
#41 | 2008-08-07Interleaved voltage controlled oscillator
#42 | 2008-07-24Method and apparatus for measuring the duty cycle of a digital signal
#43 | 2008-06-19System for automatically selecting intermediate power supply voltages for intermediate level shifters
#44 | 2008-06-12Extracting a Maximum Pulse Width of a Pulse Width Limiter
#45 | 2008-05-29Automatic Calibration of a Reference Voltage
#46 | 2008-05-15Digital circuit to measure and/or correct duty cycles
#47 | 2008-03-13DMAC Address Translation Miss Handling Mechanism
#48 | 2008-01-24Interleaved voltage controlled oscillator
#49 | 2008-01-17Duty cycle correction circuit whose operation is largely independent of operating voltage and process
#50 | 2007-12-27Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance
#51 | 2007-12-27Method for controlling operation of microprocessor which performs duty cycle correction process
#52 | 2007-11-22Method and apparatus for measuring the relative duty cycle of a clock signal
#53 | 2007-11-22Method and apparatus for measuring the duty cycle of a digital signal
#54 | 2007-11-15Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode
#55 | 2007-11-08Duty Cycle Measurement Apparatus and Method
#56 | 2007-11-01Method and apparatus for on-chip duty cycle measurement
#57 | 2007-11-01Method and apparatus for correcting the duty cycle of a digital signal
#58 | 2007-10-11Apparatus and method for extracting a maximum pulse width of a pulse width limiter
#59 | 2007-06-07Method and Apparatus for Semi-Automatic Extraction and Monitoring of Diode Ideality in a Manufacturing Environment
#60 | 2007-05-10Level shifter apparatus and method for minimizing duty cycle distortion
#61 | 2007-05-03Duty cycle measurement apparatus and method
#62 | 2007-04-12DMAC translation mechanism
#63 | 2007-04-12Apparatus and method for providing a reprogrammable electrically programmable fuse
#64 | 2007-04-05Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance
#65 | 2007-04-05Level shifter system and method to minimize duty cycle error due to voltage differences across power domains
#66 | 2007-04-05Thermal sensing method and apparatus using existing ESD devices
#67 | 2007-03-29Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer
#68 | 2007-03-29Method and apparatus for detecting frequency lock in a system including a frequency synthesizer
#69 | 2007-03-15Apparatus and method for verifying glitch-free operation of a multiplexer
#70 | 2007-01-11Self-biased high speed level shifter circuit
#71 | 2007-01-04System and method for examining high-frequency clock-masking signal patterns at full speed
#72 | 2007-01-04System and method automatically selecting intermediate power supply voltages for intermediate level shifters
#73 | 2006-10-19System and method for on/off-chip characterization of pulse-width limiter outputs
#74 | 2006-09-21Digital circuit to measure and/or correct duty cycles
#75 | 2006-08-24System and method for automatic calibration of a reference voltage
#76 | 2006-06-01High frequency circuit capable of error detection and correction of code patterns running at full speed
#77 | 2006-05-18Method and apparatus for semi-automatic extraction and monitoring of diode ideality in a manufacturing environment
#78 | 2006-05-04Circuit for minimizing filter capacitance leakage induced jitter in phase locked loops (PPLs)
#79 | 2006-04-04Method and apparatus for use in booth-encoded multiplication
#80 | 2006-02-02Read/write methods for limited memory access applications
#81 | 2005-07-28Systems and methods for operating logic circuits
#82 | 2005-06-23Round robin selection logic improves area efficiency and circuit speed
#83 | 2005-05-26Controlling bandwidth reservations method and apparatus
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