HAIFA
Israel
61
2019-02-28
The entities that hold a legal rights for patent applications filed by inventor SHEAFFER GAD:
GAD SHEAFFER from HAIFA, IL has applied for patents for these inventions. The list has both pending applications and granted patents:
PRE-POST RETIRE HYBRID HARDWARE LOCK ELISION (HLE) SCHEME
#2 | 2016-12-22DETERMINING A WRITE OPERATION
#3 | 2016-07-28Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode
#4 | 2016-06-02Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform
#5 | 2016-02-11Determining a write operation
#6 | 2015-05-14Mechanisms to accelerate transactions using buffered stores
#7 | 2015-03-12Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
#8 | 2015-02-05Handling Operating System (Os) Transitions In An Unbounded Transactional Memory (Utm) Mode
#9 | 2014-10-30Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache hierarchy
#10 | 2014-01-23Technique for using memory attributes
#11 | 2013-11-14Digital relay for out of network devices
#12 | 2013-09-12Efficient garbage collection and exception handling in a hardware accelerated transactional memory system
#13 | 2013-08-08Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
#14 | 2013-07-11Obscuring memory access patterns in conjunction with deadlock detection or avoidance
#15 | 2013-02-21Mechanisms to accelerate transactions using buffered stores
#16 | 2013-02-21Mechanisms to accelerate transactions using buffered stores
#17 | 2013-02-21Mechanisms to accelerate transactions using buffered stores
#18 | 2013-01-03Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform
#19 | 2012-11-08Operating system virtual memory management for hardware transactional memory
#20 | 2012-07-12Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM
#21 | 2012-06-21Memory model for hardware attributes within a transactional memory system
#22 | 2012-05-10Read and write monitoring attributes in transactional memory (TM) systems
#23 | 2012-03-29Performing mode switching in an unbounded transactional memory (UTM) system
#24 | 2011-08-25Protected cache architecture and secure programming paradigm to protect applications
#25 | 2011-06-16Accelerating unbounded memory transactions using nested cache resident transactions
#26 | 2011-06-16Debugging mechanisms in a cache-based memory isolation system
#27 | 2011-06-16Performing mode switching in an unbounded transactional memory (UTM) system
#28 | 2011-06-16Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode
#29 | 2011-06-16Leveraging memory isolation hardware technology to efficiently detect race conditions
#30 | 2011-06-16Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata
#31 | 2011-06-16Mechanisms to accelerate transactions using buffered stores
#32 | 2011-06-16Instrumentation of hardware assisted transactional memory system
#33 | 2011-06-16Efficient garbage collection and exception handling in a hardware accelerated transactional memory system
#34 | 2010-12-30Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers
#35 | 2010-12-30Performing escape actions in transactions
#36 | 2010-12-30Private memory regions and coherence optimizations
#37 | 2010-12-30FLEXIBLE READ- AND WRITE-MONITORED AND BUFFERED MEMORY BLOCKS
#38 | 2010-12-30Wait loss synchronization
#39 | 2010-12-30Operating system virtual memory management for hardware transactional memory
#40 | 2010-12-30Metaphysically addressed cache metadata
#41 | 2010-08-26Software filtering in a transactional memory system
#42 | 2010-07-01Registering a user-handler in hardware for transactional memory event handling
#43 | 2010-07-01Extending cache coherency protocols to support locally buffered data
#44 | 2010-07-01Memory model for hardware attributes within a transactional memory system
#45 | 2010-07-01Read and write monitoring attributes in transactional memory (TM) systems
#46 | 2010-07-01Metaphysical address space for holding lossy metadata in hardware
#47 | 2010-01-14Selective hardware lock disabling
#48 | 2009-07-02Obscuring memory access patterns in conjunction with deadlock detection or avoidance
#49 | 2009-03-12Live lock free priority scheme for memory transactions in transactional memory
#50 | 2009-01-01Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM
#51 | 2008-11-18N-wide add-compare-select instruction
#52 | 2008-08-28Selective hardware lock disabling
#53 | 2008-06-19Protecting private data from cache attacks
#54 | 2008-06-05Protected cache architecture and secure programming paradigm to protect applications
#55 | 2007-11-06Variable width, at least six-way addition/accumulation instructions
#56 | 2007-08-21Addressing mode and/or instruction for providing sine and cosine value pairs
#57 | 2007-07-05Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
#58 | 2007-05-31Acceleration threads on idle OS-visible thread execution units
#59 | 2006-04-11Multi-way select instructions using accumulated condition codes
#60 | 2005-12-13Method and apparatus for implementing single/dual packed multi-way addition instructions having accumulation options
#61 | 2005-07-07Mechanism to exploit synchronization overhead to improve multithreaded performance
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