BELLEVUE, Washington
United States
44
2019-10-10
The entities that hold a legal rights for patent applications filed by inventor GRAY JAN:
JAN GRAY from BELLEVUE, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Decoupled processor instruction window and operand buffer
#2 | 2016-12-29Age-based management of instruction blocks in a processor instruction window
#3 | 2016-12-29Explicit instruction scheduler state information for a processor
#4 | 2016-12-29Bulk allocation of instruction blocks to a processor instruction window
#5 | 2016-12-29Decoding information about a group of instructions including a size of the group of instructions
#6 | 2016-12-29Mapping instruction blocks based on block size
#7 | 2016-12-29Decoupled processor instruction window and operand buffer
#8 | 2016-07-28Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode
#9 | 2015-09-17Parallel decision tree processor architecture
#10 | 2015-09-17DECISION TREE PROCESSORS
#11 | 2015-09-17DECISION TREE THRESHOLD CODING
#12 | 2015-02-05Handling Operating System (Os) Transitions In An Unbounded Transactional Memory (Utm) Mode
#13 | 2014-10-30Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache hierarchy
#14 | 2013-09-12Efficient garbage collection and exception handling in a hardware accelerated transactional memory system
#15 | 2013-02-21Mechanisms to accelerate transactions using buffered stores
#16 | 2013-02-21Mechanisms to accelerate transactions using buffered stores
#17 | 2013-02-21Mechanisms to accelerate transactions using buffered stores
#18 | 2012-11-08Operating system virtual memory management for hardware transactional memory
#19 | 2012-03-29Performing mode switching in an unbounded transactional memory (UTM) system
#20 | 2011-11-17Parallelizing sequential frameworks using transactions
#21 | 2011-06-16Debugging mechanisms in a cache-based memory isolation system
#22 | 2011-06-16Performing mode switching in an unbounded transactional memory (UTM) system
#23 | 2011-06-16Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode
#24 | 2011-06-16Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata
#25 | 2011-06-16Mechanisms to accelerate transactions using buffered stores
#26 | 2011-06-16Instrumentation of hardware assisted transactional memory system
#27 | 2011-06-16Efficient garbage collection and exception handling in a hardware accelerated transactional memory system
#28 | 2010-12-30Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers
#29 | 2010-12-30Performing escape actions in transactions
#30 | 2010-12-30Private memory regions and coherence optimizations
#31 | 2010-12-30FLEXIBLE READ- AND WRITE-MONITORED AND BUFFERED MEMORY BLOCKS
#32 | 2010-12-30Wait loss synchronization
#33 | 2010-12-30Operating system virtual memory management for hardware transactional memory
#34 | 2010-12-30Metaphysically addressed cache metadata
#35 | 2010-12-30Hardware accelerated transactional memory system with open nested transactions
#36 | 2010-08-26Software filtering in a transactional memory system
#37 | 2008-05-22Parallelizing sequential frameworks using transactions
#38 | 2008-05-22Parallelizing sequential frameworks using transactions
#39 | 2008-02-14Cache metadata identifiers for isolation and sharing
#40 | 2007-10-18Software accessible cache metadata
#41 | 2007-10-18Cache metadata for accelerating software transactional memory
#42 | 2007-10-18Cache metadata for implementing bounded transactional memory
#43 | 2007-05-22Cache residency test instruction
#44 | 2005-09-01Code rewriting
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