Beaverton, Oregon
United States
30
2017-04-06
The entities that hold a legal rights for patent applications filed by inventor Greiner Robert J.:
Robert J. Greiner from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Launching a secure kernel in a multiprocessor system
#2 | 2016-03-03Launching a secure kernel in a multiprocessor system
#3 | 2015-02-26Launching a secure kernel in a multiprocessor system
#4 | 2013-09-26Launching a secure kernel in a multiprocessor system
#5 | 2013-09-05Dynamic voltage transitions
#6 | 2013-04-04Frequency synthesis methods and systems
#7 | 2013-02-28Integrating intellectual property (IP) blocks into a processor
#8 | 2013-02-21Dynamic voltage transitions
#9 | 2012-09-20Launching a secure kernel in a multiprocessor system
#10 | 2010-11-04Launching a secure kernel in a multiprocessor system
#11 | 2010-10-14Launching a secure kernel in a multiprocessor system
#12 | 2010-07-08Communicating via an in-die interconnect
#13 | 2010-06-03Power control unit with digitally supplied system parameters
#14 | 2008-06-26Launching a secure kernel in a multiprocessor system
#15 | 2008-05-29Voltage regulator with loadline based mostly on dynamic current
#16 | 2008-05-08Launching a secure kernel in a multiprocessor system
#17 | 2008-05-08Launching a secure kernel in a multiprocessor system
#18 | 2008-05-08Launching a secure kernel in a multiprocessor system
#19 | 2007-11-29Method and an apparatus to sense supply voltage
#20 | 2007-11-15Multi-phase voltage regulator with phases ordered by lowest phase current
#21 | 2007-11-15Power control unit with digitally supplied system parameters
#22 | 2007-11-08Technique to modify a timer
#23 | 2007-01-04Virtualization of pin functionality in a point-to-point interface
#24 | 2005-12-08Processor temperature control interface
#25 | 2005-12-08Launching a secure kernel in a multiprocessor system
#26 | 2005-12-08Multi-node chipset lock flow with peer-to-peer non-posted I/O requests
#27 | 2005-10-18Processor temperature control interface
#28 | 2005-06-14Enhanced highly pipelined bus architecture
#29 | 2005-04-12System and method for communicating device information between a device and a controller
#30 | 2005-04-12Snoop phase in a highly pipelined bus architecture
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