Inventor profile of:

Loic Pallardy

City:

Rouillon

Country:

France

Published Applications:

25

Last publication date:

2025-12-04

Top Assignees for applications by Loic Pallardy

The entities that hold a legal rights for patent applications filed by inventor Pallardy Loic:

Recent patent applications by Pallardy Loic

Loic Pallardy from Rouillon, FR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-12-04
US20250371195A1
Physics

METHOD FOR EXECUTING A SOFTWARE PROGRAM BY A PROCESSING UNIT COMPRISING A COMPILATION PHASE

#2 | 2025-02-13
US20250053318A1
Physics

DYNAMIC MANAGEMENT OF A MEMORY FIREWALL

#3 | 2024-12-05
US20240406163A1
Electricity

METHOD FOR MANAGING THE LIFE CYCLE OF A SYSTEM-ON-CHIP, AND CORRESPONDING SYSTEM-ON-CHIP

#4 | 2024-11-07
US20240370382A1
Physics

SYSTEM-ON-CHIP HAVING A MEMORY CONTROLLER AND CORRESPONDING MEMORY CONTROL METHOD

#5 | 2024-09-26
US20240320359A1
Physics

SYSTEM-ON-CHIP INCLUDING RESOURCE ISOLATION FRAMEWORK AND COUNTERMEASURE CIRCUIT, AND CORRESPONDING METHOD

#6 | 2024-07-25
US20240248864A1
Physics

CONNECTION CIRCUIT FOR MEMORY ACCESSES

#7 | 2024-05-30
US20240176689A1
Physics

METHOD FOR MANAGING THE ISOLATION OF RESOURCES OF A SYSTEM-ON-CHIP, AND CORRESPONDING SYSTEM-ON-CHIP

#8 | 2024-01-04
US20240004804A1
Physics

METHOD FOR MANAGING ACCESS RIGHTS OF MEMORY REGIONS AND CORRESPONDING SYSTEM ON CHIP

#9 | 2023-10-26
US20230342279A1
Physics

METHOD FOR MONITORING AN EXECUTION OF A PROGRAM CODE PORTION AND CORRESPONDING SYSTEM-ON-CHIP

#10 | 2023-09-14
US20230291645A1
Electricity

Method for managing the operation of a system on chip, and corresponding system on chip

#11 | 2023-05-25
US20230161863A1
Physics

METHOD FOR EXECUTING A SOFTWARE PROGRAM BY A PROCESSING UNIT COMPRISING A COMPILATION PHASE

#12 | 2023-05-25
US20230161486A1
Physics

METHOD FOR MANAGING A MEMORY IN A SYSTEM-ON-A-CHIP

#13 | 2023-05-25
US20230161485A1
Physics

MANAGEMENT OF A MEMORY FIREWALL IN A SYSTEM ON CHIP

#14 | 2023-05-25
US20230161484A1
Physics

Dynamic management of a memory firewall

#15 | 2023-01-19
US20230015027A1
Physics

METHOD OF MANAGING ACCESS RIGHTS FOR SOFTWARE TASKS EXECUTED BY A MICROCONTROLLER, AND CORRESPONDING INTEGRATED CIRCUIT

#16 | 2022-06-09
US20220179659A1
Physics

Method of resetting a master device of a system on chip and corresponding system on chip

#17 | 2022-05-26
US20220164016A1
Physics

Management of a low-power mode

#18 | 2022-05-19
US20220156217A1
Physics

METHOD FOR MANAGING THE OPERATION OF A SYSTEM ON CHIP, AND CORRESPONDING SYSTEM ON CHIP

#19 | 2021-05-27
US20210160193A1
Electricity

Method for managing the configuration of access to peripherals and their associated resources of a system on chip, and corresponding system on chip

#20 | 2021-05-27
US20210160134A1
Electricity

Method for managing the operation of a system on chip, and corresponding system on chip

#21 | 2021-05-27
US20210157668A1
Physics

Method for managing the debugging of a system on chip forming for example a microcontroller, and corresponding system on chip

#22 | 2020-12-17
US20200394047A1
Physics

Method and device for managing operation of a computing unit capable of operating with instructions of different sizes

#23 | 2015-05-21
US20150143072A1
Physics

Method in a memory management unit for managing address translations in two stages

#24 | 2015-01-22
US20150026399A1
Physics

Automatic partial array self-refresh

#25 | 2012-08-23
US20120215975A1
Physics

Dynamic management of random access memory

InventorID:

1046337 ⎘