STMICROELECTRONICS INTERNATIONAL N.V.

Data volume sculptor for deep learning acceleration

Arithmetic unit for deep learning acceleration

System and method to increase display area utilizing a plurality of discrete displays

Dual port memory cell with improved access resistance

Physically unclonable function device

LED control and driving circuit capable of both analog and digital dimming

Multi-fingered diode with reduced capacitance and method of making the same

Dual port memory cell with improved access resistance

Lead frame surface finishing

On-chip resistor trimming to compensate for process variation

System and method to increase display area utilizing a plurality of discrete displays

Context awareness of a smart device through sensing transient and continuous events

Data volume sculptor for deep learning acceleration

Latch-up immunization techniques for integrated circuits

LED control and driving circuit capable of both analog and digital dimming

Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

Low leakage MOSFET supply clamp for electrostatic discharge (ESD) protection

Method of operating a low dropout regulator by selectively removing and replacing a DC bias from a power transistor within the low dropout regulator

Functional safety method, corresponding system-on-chip, device and vehicle

Support substrates for microfluidic die

Reconfigurable interconnect

Circuit and method for at speed detection of a word line fault condition in a memory circuit

Low power crystal oscillator

Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory

Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory

Method for generating a personalized classifier for human motion activities of a mobile or wearable device user with unsupervised learning

Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory

Radio-frequency identification transponder and method for data transmission by means of radio-frequency identification technology

Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator

Frequency synthesizer with dynamically selected level shifting of the oscillating output signal

Process compensated gain boosting voltage regulator

On-chip resistor trimming to compensate for process variation

Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop

Circuit for detecting damage to a peripheral edge on an integrated circuit die

Test circuit for electronic device permitting interface control between two supply stacks in a production test of the electronic device

Robust adaptive method and circuit for controlling a timing window for enabling operation of sense amplifier

Locked loop circuit with reference signal provided by un-trimmed oscillator

Multi-fingered diode with reduced capacitance and method of making the same

Sub-bandgap compensated reference voltage generation circuit

Combinatorial serial and parallel test access port selection in a JTAG interface

Low voltage differential signaling fault detector

RC oscillator watchdog circuit

Soft error-resilient latch

Latch-up immunization techniques for integrated circuits

Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

Digital sinusoid generator

Control circuitry for increasing power output in quasi-resonant converters

Method for a phase calibration in a frontend circuit of a near field communication device

Driving circuit using buck converter capable of generating sufficient voltage to power a LED circuit and associated auxiliary circuitry in a normal mode of operation, and insufficient to power the LED circuit but sufficient to power the associated auxiliary circuitry in an off mode of operation

Phase locked loop design with reduced VCO gain

Sequential test access port selection in a JTAG interface

Level shifting circuit with conditional body biasing of transistors

Integrated silicon controlled rectifier (SCR) and a low leakage SCR supply clamp for electrostatic discharge (ESP) protection

Low leakage MOSFET supply clamp for electrostatic discharge (ESD) protection

Memory architecture including response manager for error correction circuit

Biasing cascode transistors of an output buffer circuit for operation over a wide range of supply voltages

Radio-frequency identification transponder and method for data transmission by means of radio-frequency identification technology

Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop

Lead frame surface finishing

Method and circuit for adaptive read-write operation in self-timed memory

Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof

Data volume sculptor for deep learning acceleration

Arithmetic unit for deep learning acceleration

Acceleration unit for a deep learning engine

Processing system, related integrated circuit, device and method

Context awareness of a smart device through sensing transient and continuous events

Support substrates for microfluidic die

Support substrates for microfluidic die

Level shifting circuit with conditional body biasing of transistors

Carrier frequency offset compensation circuit and process for a communications receiver

Microphone array auto-directive adaptive wideband beamforming using orientation information from MEMS sensors

Methods and techniques for reducing latency in changing channels in a digital video environment

Dual port memory cell with improved access resistance

High operation frequency, area efficient and cost effective content addressable memory architecture

Latency buffer circuit with adaptable time shift

Full swing positive to negative MOSFET supply clamp for electrostatic discharge (ESD) protection

LED control and driving circuit capable of both analog and digital dimming

Power supply clamp for electrostatic discharge (ESD) protection having a circuit for controlling clamp time out behavior

Video encoders/decoders and video encoding/decoding methods for video surveillance applications

High performance I2C transmitter and bus supply independent receiver, supporting large supply voltage variations

Glitch immune cascaded integrator comb architecture for higher order signal interpolation

Circuit for determining whether an actual transmission was received in a low-voltage differential sensing receiver

Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)

Two-point modulator with matching gain calibration

Method and circuit for adaptive read-write operation in self-timed memory

High range positive voltage level shifter using low voltage devices

Memory architecture including response manager for error correction circuit

Low area parallel checker for multiple test patterns

Low voltage, master-slave flip-flop

Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

Low leakage low dropout regulator with high bandwidth and power supply rejection, and associated methods

Calibration of a voltage controlled oscillator to trim the gain thereof, using a phase locked loop and a frequency locked loop

Voltage level monitoring of an integrated circuit for production test and debug

Voltage regulator bypass circuitry usable during device testing operations

Circuitry for testing non-maskable voltage monitor for power management block