Leander, Texas
United States
58
2024-08-01
The entities that hold a legal rights for patent applications filed by inventor Obradovic Borna J.:
Borna J. Obradovic from Leander, US has applied for patents for these inventions. The list has both pending applications and granted patents:
HIGH-DENSITY NEUROMORPHIC COMPUTING ELEMENT
#2 | 2023-06-29High-density neuromorphic computing element
#3 | 2023-01-05Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs
#4 | 2021-04-22Monolithic multi-bit weight cell for neuromorphic computing
#5 | 2021-02-25High-density neuromorphic computing element
#6 | 2020-12-03Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
#7 | 2020-09-03Field effect transistor with decoupled channel and methods of manufacturing the same
#8 | 2020-07-23Method of enabling sparse neural networks on memresistive accelerators
#9 | 2020-04-23Low current leakage finFET and methods of making the same
#10 | 2020-04-23FinFET with reduced extension resistance and methods of manufacturing the same
#11 | 2020-02-27Method for selectively increasing silicon fin area for vertical field effect transistors
#12 | 2019-12-19Method of forming multi-threshold voltage devices and devices so formed
#13 | 2019-10-31Method and system for training of neural networks using continuously differentiable models
#14 | 2019-10-17MOS DEVICE WITH STRONG POLARIZATION COUPLING
#15 | 2019-10-17Ferroelectric-based memory cell usable in on-logic chip memory
#16 | 2019-10-17Memory device with strong polarization coupling
#17 | 2019-09-12FE-FET-based XNOR cell usable in neuromorphic computing
#18 | 2019-06-13Dielectric separation of partial GAA FETs
#19 | 2019-05-23Bi-directional weight cell
#20 | 2019-05-16Field effect transistor with decoupled channel and methods of manufacturing the same
#21 | 2019-05-16Method for selectively increasing silicon fin area for vertical field effect transistors
#22 | 2019-05-02Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing
#23 | 2019-05-02Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed
#24 | 2019-04-25Method of forming multi-threshold voltage devices and devices so formed
#25 | 2019-03-14Method and system for performing analog complex vector-matrix multiplication
#26 | 2019-03-14Selectorless 3D stackable memory
#27 | 2019-01-24VARIABLE PRECISION NEUROMORPHIC ARCHITECTURE
#28 | 2019-01-10Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs
#29 | 2018-10-18Monolithic multi-bit weight cell for neuromorphic computing
#30 | 2018-10-04Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
#31 | 2018-06-21High-density neuromorphic computing element
#32 | 2018-06-14Field effect transistor with decoupled channel and methods of manufacturing the same
#33 | 2018-05-10Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
#34 | 2018-04-26Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
#35 | 2018-02-22Horizontal nanosheet FETs and method of manufacturing the same
#36 | 2018-02-22Low power analog or multi-level memory for neuromorphic computing
#37 | 2017-11-23Method of forming internal dielectric spacers for horizontal nanosheet FET architectures
#38 | 2017-09-21FET including an InGaAs channel and method of enhancing performance of the FET
#39 | 2017-09-14Structure and method to achieve compressively strained Si NS
#40 | 2017-05-25Stacked independently contacted field effect transistor having electrically separated first and second gates
#41 | 2017-05-25Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance
#42 | 2017-04-06Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same
#43 | 2017-04-040T bi-directional memory cell
#44 | 2016-10-20Multi-layer fin field effect transistor devices and methods of forming the same
#45 | 2016-06-16Integrated circuit devices including source/drain extension regions and methods of forming the same
#46 | 2016-06-09Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same
#47 | 2016-04-21Strained stacked nanosheet FETS and/or quantum well stacked nanosheet
#48 | 2016-04-21Strained stacked nanosheet FETs and/or quantum well stacked nanosheet
#49 | 2016-04-14Methods of forming semiconductor devices including conductive contacts on source/drains
#50 | 2015-12-17Integrated circuit chips having field effect transistors with different gate designs
#51 | 2015-12-17Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width
#52 | 2015-10-15Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same
#53 | 2015-08-27Integrated circuit devices including FinFETs and methods of forming the same
#54 | 2015-05-28FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
#55 | 2015-05-07Quantum interference based logic devices including electron monochromator
#56 | 2015-05-07Crystalline multiple-nanosheet III-V channel FETs
#57 | 2015-04-02Integrated circuit devices including FinFETS and methods of forming the same
#58 | 2015-02-05FinFET devices including recessed source/drain regions having optimized depths
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