Markham
Canada
33
2024-02-01
The entities that hold a legal rights for patent applications filed by inventor Topacio Roden R.:
Roden R. Topacio from Markham, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
SEMICONDUCTOR ASSEMBLY INCLUDING MULTIPLE SOLDER MASKS
#2 | 2017-04-20Semiconductor chip with patterned underbump metallization and polymer film
#3 | 2015-11-26Methods of fabricating semiconductor chip solder structures
#4 | 2015-10-01Semiconductor chip with patterned underbump metallization and polymer film
#5 | 2015-10-01Interconnect etch with polymer layer edge protection
#6 | 2013-10-03SEMICONDUCTOR CHIP DEVICE WITH FRAGMENTED SOLDER STRUCTURE PADS
#7 | 2013-06-13HEATSINK INTERPOSER
#8 | 2013-05-09SEMICONDUCTOR SUBSTRATE WITH MOLDED SUPPORT LAYER
#9 | 2013-03-14Solder mask with anchor structures
#10 | 2013-02-28Methods of fabricating semiconductor chip solder structures
#11 | 2012-12-27SEMICONDUCTOR CHIP WITH DUAL POLYMER FILM INTERCONNECT STRUCTURES
#12 | 2012-10-18SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION
#13 | 2012-09-27Method of fabricating a semiconductor chip with supportive terminal pad
#14 | 2012-05-24Integrated circuit package strip with stiffener
#15 | 2012-01-19Methods of forming semiconductor chip underfill anchors
#16 | 2011-09-22Method of manufacturing substrates having asymmetric buildup layers
#17 | 2011-09-15CIRCUIT BOARD WITH ANCHORED UNDERFILL
#18 | 2011-09-15Methods of forming semiconductor chip underfill anchors
#19 | 2011-06-09Conductor bump method and apparatus
#20 | 2011-03-10Semiconductor Chip with Stair Arrangement Bump Structures
#21 | 2011-03-03Semiconductor chip with contoured solder structure opening
#22 | 2010-12-16Semiconductor chip passivation structures and methods of making the same
#23 | 2010-06-24Face-to-face (F2F) hybrid structure for an integrated circuit
#24 | 2010-06-10Semiconductor chip bump connection apparatus and method
#25 | 2010-04-29Hybrid Semiconductor Chip Package
#26 | 2010-02-25Integrated circuit package employing predetermined three-dimensional solder pad surface and method for making same
#27 | 2010-01-07Semiconductor chip passivation structures and methods of making the same
#28 | 2009-11-12Semiconductor chip bump connection apparatus and method
#29 | 2009-02-05Under Bump Routing Layer Method and Apparatus
#30 | 2009-02-05Conductor bump method and apparatus
#31 | 2008-08-21Integrated package circuit with stiffener
#32 | 2008-07-17ANCHOR STRUCTURE FOR AN INTEGRATED CIRCUIT
#33 | 2008-03-06Flip-Chip Ball Grid Array Strip and Package
108406 ⎘