ADVANCED MICRO DEVICES, INC.

Hardware assisted memory profiling aggregator

Dedicated interface for coupling flash memory and dynamic random access memory

Integrated circuit module with integrated discrete devices

Methods and devices for testing multiple memory configurations

Reconfigurable virtual graphics and compute processor pipeline

Pipeline including separate hardware data paths for different instruction types

System and method for scheduling instructions in a multithread SIMD architecture with a fixed number of registers

Low latency wireless Virtual Reality systems and methods

System and method for protecting GPU memory instructions against faults

Method and system for yield operation supporting thread-like behavior

Method and apparatus for performing processing in a camera

High dynamic range for head-mounted display device

Fine-grained speed binning in an accelerated processing device

Hybrid render with deferred primitive batch binning

Power efficient retraining of memory accesses

Computational optics

Illumination control techniques for color and IR camera sensors

Variable rate shading

Method and apparatus of performing a memory operation in a hierarchical memory assembly

Device and method for compressing panoramic video images

Buffer management for plug-in architectures in computation graph structures

Method and apparatus for memory vulnerability prediction

Monitor support on accelerated processing device

Bandwidth saving architecture for scalable video coding spatial mode

Protecting host memory from access by untrusted accelerators

Hang detection for virtualized accelerated processing device

Cache aware self-referential structure peeling

Processor with host and slave operating modes stacked with memory

Early virtualization context switch for virtualized accelerated processing device

Virtual FPGA management and optimization system

Transmission of large messages in computer systems

Method and apparatus of image processing

Method and apparatus of integrating memory stacks

Policies for shader resource allocation in a shader core

Method and apparatus of seam finding

System and method for application migration for a dockable device

Network cache injection for coherent GPUs

Memory protection in highly parallel computing hardware

Page migration with varying granularity

Hierarchical power distribution in large scale computing systems

Dynamic memory remapping to reduce row-buffer conflicts

Streaming translation lookaside buffer

Sharing translation lookaside buffer resources for different traffic classes

Data compression with inline compression metadata

Fused shader programs

Out of order pixel shader exports

Method and apparatus for asynchronous scheduling

Split frame rendering

Configurable skewed associativity in a translation lookaside buffer

Waterfall counters and an application to architectural vulnerability factor estimation

High-speed selective cache invalidates and write-backs on GPUS

Method and apparatus for integration of non-volatile memory

Method and apparatus of copying data to remote memory

Removing or identifying overlapping fragments after z-culling

Out-of-order cache returns

Tag and data organization in large memory caches

Operation cache

Identifying duplicate indices in an input index stream

Detecting buffer overflows in general-purpose GPU applications

Identifying primitives in input index system

Method and system for yield operation supporting thread-like behavior

Method and apparatus for power reduction in a multi-threaded mode

Pairing SIMD lanes to perform double precision operations

Software mode register access for platform margining and debug

GPU remote communication with triggered operations

Scoped persistence barriers for non-volatile memories

Dynamic reload of video encoder motion estimation search window under performance/power constraints

Combined world-space pipeline shader stages

Primitive shader

Method and apparatus for masking and transmitting data

Techniques for handling cache coherency traffic for contended semaphores

Network interface controller-based scheduling of processing tasks in a distributed computing system

Ring buffer including a preload buffer

Lock address contention predictor

Dynamic configuration of inter-chip and on-chip networks in cloud computing system

Method and apparatus for compressing randomly accessed data

Speculative retirement of post-lock instructions

System and method for efficient pointer chasing

Light-weight cache coherence for data processors with limited data sharing

Heterogeneous parallel primitives programming model

Method and device for determining branch prediction history for branch prediction by partially combining shifted branch prediction history with branch signature

Branch target buffer compression

Computer-based square root and division operations

Low power adaptive synchronizer

Method and apparatus for compressing addresses

Tracking stores and loads by bypassing load store units

Updating least-recently-used data for greater persistence of higher generality cache entries

System and method for load and store queue allocations at address generation time

Paired value comparison for redundant multi-threading operations

Primitive culling using automatically compiled compute shaders

Memory controller with flexible address decoding