Dallas, Texas
United States
40
2023-04-27
The entities that hold a legal rights for patent applications filed by inventor BONIFIELD Thomas D.:
Thomas D. BONIFIELD from Dallas, US has applied for patents for these inventions. The list has both pending applications and granted patents:
HYBRID ISOLATION CAPACITORS IN SERIES
#2 | 2021-11-25Device isolator with reduced parasitic capacitance
#3 | 2021-05-13Integrated capacitor with sidewall having reduced roughness
#4 | 2020-02-20Hydrogen ventilation of CMOS wafers
#5 | 2019-12-12Hybrid high and low stress oxide embedded capacitor dielectric
#6 | 2019-06-27Method of fabricating a thick oxide feature on a semiconductor wafer
#7 | 2019-06-20Generating multi-focal defect maps using optical tools
#8 | 2019-05-16Device isolator with reduced parasitic capacitance
#9 | 2019-03-07High voltage galvanic isolation device
#10 | 2018-05-10Integrated capacitor with sidewall having reduced roughness
#11 | 2018-01-25Device isolator with reduced parasitic capacitance
#12 | 2017-10-26Methods and apparatus for high voltage integrated circuit capacitors
#13 | 2017-09-14High voltage galvanic isolation device
#14 | 2017-03-02Methods and apparatus for high voltage integrated circuit capacitors
#15 | 2016-12-29SEMICONDUCTOR WIRE BONDING AND METHOD
#16 | 2016-10-13Device isolator with reduced parasitic capacitance
#17 | 2016-06-16High breakdown voltage microelectronic device isolation structure with improved reliability
#18 | 2016-06-09High breakdown voltage microelectronic device isolation structure with improved reliability
#19 | 2016-05-12Methods and apparatus for high voltage integrated circuit capacitors
#20 | 2016-05-12Scribe seals and methods of making
#21 | 2015-11-19High breakdown voltage microelectronic device isolation structure with improved reliability
#22 | 2015-03-05Crack deflector structure for improving semiconductor device robustness against saw-induced damage
#23 | 2012-08-09IC device having low resistance TSV comprising ground connection
#24 | 2012-08-02IC device having low resistance TSV comprising ground connection
#25 | 2011-01-27TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices
#26 | 2010-05-06Crack deflector structure for improving semiconductor device robustness against saw-induced damage
#27 | 2009-12-31Scribe seal connection
#28 | 2009-11-26Mask overhang reduction or elimination after substrate etch
#29 | 2009-11-12Packaged electronic devices with face-up die having TSV connection to leads and die pad
#30 | 2009-11-12IC device having low resistance TSV comprising ground connection
#31 | 2009-11-12TSVS having chemically exposed TSV tips for integrated circuit devices
#32 | 2008-12-18P-DOPED REGION WITH IMPROVED ABRUPTNESS
#33 | 2008-06-05Nickel alloy silicide including indium and a method of manufacture therefor
#34 | 2007-06-21Nickel silicide including indium and a method of manufacture therefor
#35 | 2007-03-01Nickel alloy silicide including indium and a method of manufacture therefor
#36 | 2006-10-05Nickel silicide including indium and a method of manufacture therefor
#37 | 2006-02-02Method for reducing metal silicide excessive encroachment defects in the manufacture of a semiconductor device having silicided source/drain regions
#38 | 2006-02-02Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing
#39 | 2006-02-02Method for manufacturing a semiconductor device having silicided regions
#40 | 2005-11-22Method for fabricating a multi-level integrated circuit having scatterometry test structures stacked over same footprint area
1084113 ⎘