TEXAS INSTRUMENTS, INC.

Line receiver circuit with active termination

Synthesizing graphene from metal-carbon solutions using ion implantation

DMOS transistor having an increased breakdown voltage and method for production

System and method for estimating a transmit channel response and/or a feedback channel response using frequency shifting

Low-power data loop recorder

Dynamic RAM

Method of manufacturing a semiconductor device having improved transistor performance

Graphene synthesis by chemical vapor deposition

Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes

Synthesizing graphene from metal-carbon solutions using ion implantation

Frame structure for medium access in body area networks (BAN)

Pairwise temporal key creation for secure networks

Authentication and encryption for secure data transmission

Smart adjustment of backoff counter and contention window for improved random access

Mitigation of interference between wireless networks

Access and power management for centralized networks

Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene

IC having TSV arrays with reduced TSV induced stress

Gate dielectric first replacement gate processes and integrated circuits therefrom

Circuit and method of output power detection for a converter circuit

Noise injection circuit and method for signal processing

Short circuit monitor for current set resistor

Combined metallic bonding and molding for electronic assemblies including void-reduced underfill

Mask overhang reduction or elimination after substrate etch

Packaged electronic devices with face-up die having TSV connection to leads and die pad

IC device having low resistance TSV comprising ground connection

TSVS having chemically exposed TSV tips for integrated circuit devices

Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric

Via-node-based electromigration rule-check methodology

Ferroelectric capacitor manufacturing process

Semiconductor device having wafer level chip scale packaging substrate decoupling

Method and system for controlling spatial light modulator interface buses

Use of dopants to provide low defect gate full silicidation

Systems and methods for kickback reduction in an ADC

System and method for enhancing I2C bus data rate

Discovery, detection, and management of daisy-chain system topology

Package stiffener and a packaged device using the same

Systems and methods for hysteresis control in a comparator

Method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder

Latched comparator and methods for using such

Parallel bipolar logic devices and methods for using such

Method and system of accessing display window memory

Token-based trace system

Method for selective deposition of a thin self-assembled monolayer

Semiconductor device with reduced diffusion of workfunction modulating element

Methods and systems for watermarking digital media

RFID power from handset transmissions

Systems and methods for multiple equation graphing

Semiconductor device made by multiple anneal of stress inducing layer

Unbalanced plural string LED driver with common return resistor

Method for forming ultra-thin low leakage multiple gate devices using a masking layer over the semiconductor substrate

Manufacturing a semiconductive device using a controlled atomic layer removal process

Semiconductive device fabricated using a substantially disassociated chlorohydrocarbon

Offset balancer, method of balancing an offset and a wireless receiver employing the balancer and the method

Digital, down-converted RF residual leakage signal mitigating RF residual leakage

Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same

Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same

Method for chemical mechanical planarization of a metal layer located over a photoresist layer and a method for manufacturing a micro pixel array using the same

Method to obtain fully silicided gate electrodes

Transistor design self-aligned to contact

Method to obtain uniform nitrogen profile in gate dielectrics

Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor

Formation of uniform silicate gate dielectrics