Inventor profile of:

Kumar Nagarajan

City:

Cupertino, California

Country:

United States

Published Applications:

15

Last publication date:

2026-05-21

Top Assignees for applications by Kumar Nagarajan

The entities that hold a legal rights for patent applications filed by inventor Nagarajan Kumar:

Recent patent applications by Nagarajan Kumar

Kumar Nagarajan from Cupertino, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-05-21
US20260141840A1
Physics

Electronic Device with a Display and a System-in-Package

#2 | 2025-10-23
US20250328010A1
Physics

Light Projector Module with Directly Bonded and Orthogonal Rigid Components

#3 | 2025-09-11
US20250286027A1
Electricity

SYSTEM PACKAGING FOR CELLULAR MODEM AND TRANSCEIVER SYSTEM OF HETEROGENEOUS STACKING

#4 | 2025-06-05
US20250183127A1
Electricity

Molded Silicon on Passive Package

#5 | 2025-03-20
US20250096096A1
Electricity

Electronic Package Molded Vertical Interconnection

#6 | 2023-07-27
US20230238365A1
Electricity

System packaging for cellular modem and transceiver system of heterogeneous stacking

#7 | 2023-06-08
US20230178458A1
Electricity

Molded silicon on passive package

#8 | 2018-01-04
US20180006003A1
Electricity

Structure and method for hybrid optical package with glass top cover

#9 | 2016-07-19
US14494880
Electricity

Sacrificial pad on semiconductor package device and method

#10 | 2015-12-31
US20150380627A1
Electricity

LID ASSEMBLY FOR THERMOPILE TEMPERATURE SENSING DEVICE IN THERMAL GRADIENT ENVIRONMENT

#11 | 2015-09-15
US14231963
Electricity

Stacked LED for optical sensor devices

#12 | 2015-08-27
US20150243824A1
Electricity

Optical sensor having a light emitter and a photodetector assembly directly mounted to a transparent substrate

#13 | 2015-08-27
US20150243590A1
Electricity

Embedded die redistribution layers for active device

#14 | 2015-04-23
US20150109785A1
Mechanical engineering

Wafer level lens in package

#15 | 2014-09-23
US13246728
-

Semiconductor structure and method for interconnection of integrated circuits

InventorID:

1135402 ⎘