XILINX, INC.

ALIGNMENT MARKERS FOR ALIGNING DL FLITS TO ETHERNET CODEWORDS

SPLIT-KEY ACCESS FOR INTEGRATED CIRCUITS WITH HARDWARE ROOTS OF TRUST

COMPILE TIME REDUCTION AND IMPROVED ROUTABILITY FOR CIRCUIT DESIGNS

DEVICES, SYSTEMS, AND METHODS FOR DIRECT CACHE INJECTION IN NETWORKING DEVICES

DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE

ACCELERATED CIRCUIT DESIGN TEST COVERAGE CLOSURE USING MACHINE-LEARNING BASED CONSTRAINT RANDOMIZATION

SUPPORTING MULTIPLE CONTROLLER CIRCUITS ON A MULTIPLEXED COMMUNICATION BUS

DATA PACKING FOR POWER AND AREA-EFFICIENT MEMORY STRUCTURES AND PERFORMANCE-EFFICIENT DECODING OF ENCODED DATA

DETECTING AND CORRECTING SINGLE EVENT UPSETS IN STATIC RANDOM-ACCESS MEMORY CELLS

AUTOMATED GENERATION OF COVERAGE DATA FOR CIRCUIT DESIGNS USING MACHINE LEARNING

LIGHT INCREMENTAL FLOW FOR QUALITY-OF-RESULT RESILIENCE

PROTOCOL ENHANCEMENTS FOR LOW LATENCY APPLICATIONS

DEVICES, SYSTEMS, AND METHODS TO OPTIMIZE POWER MANAGEMENT WITHIN IN DIE-TO-DIE INTERCONNECTS

MODEL LEVEL DEBUGGING OF MACHINE LEARNING DESIGNS ON NEURAL PROCESSING UNITS

HIGH-LEVEL SYNTHESIS GENERATION OF ARBITRARY MULTIPLEXER LOGIC

DISTRIBUTED ON-CHIP KEY-VALUE STORE CIRCUIT ARCHITECTURE

Drift-Based Margin Optimizer

In-Situ Electrical Connectivity Detection

FINE-GRAINED PREEMPTION OF A DATA FLOW ARCHITECTURE BASED NEURAL PROCESSING UNIT

OPTICAL COUPLER FOR PHOTONIC INTEGRATED CIRCUITS

COMMAND STREAM STITCHING FOR HARDWARE ACCELERATION

SYSTEMS AND METHODS FOR MANAGING ORDER OF COMMAND PROCESSING

CASCADED LOOKUP-TABLE MAPPING FOR CIRCUIT DESIGN AND IMPLEMENTATION

ACCELERATION OF CRYPTOGRAPHIC OPERATIONS

CONFIGURATION OF AN ADAPTIVE SYSTEM-ON-CHIP

CARRY CHAIN REDUCTION AND REPLACEMENT FOR CIRCUIT DESIGNS

OFFLOADING OPERATIONS USING A NETWORK INTERFACE CONTROLLER

Selectable Slice Mapping

CIRCUIT DESIGN IMPLEMENTATION FOR 3-DIMENSIONAL INTEGRATED CIRCUIT DEVICES

SYSTEMS AND METHODS FOR CARD RETENTION FEATURE RETROFIT

MEMORY DEFRAGMENTATION IN PROGRAMMABLE INTEGRATED CIRCUIT DEVICES

TRANSMISSION AND PROCESSING OF DATA IN PARALLEL SYSTEMS

MACHINE LEARNING DEPLOYMENT PLATFORM

TRANSMISSION AND PROCESSING OF DATA IN PARALLEL SYSTEMS

SYSTEMS AND METHODS FOR PROVIDING POWER INTEGRITY TO FUNCTIONAL CIRCUITRY OF A SEMICONDUCTOR DEVICE

FIREWALLING COMMUNICATION PORTS IN A MULTI-PORT SYSTEM

3D INTEGRATED CIRCUIT WITH ENHANCED DEBUGGING CAPABILITY

SECURE READBACK FROM CONFIGURATION MEMORY

MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY

LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS TO MEMORY CONTROLLERS

PROGRAMMABLE CONGESTION MONITORING AND/OR CONTROL

EMULATING A CIRCUIT DESIGN IN COMMUNICATION WITH A PERIPHERAL

ON-SITE UPDATING OF MACHINE LEARNING MODELS AND MACHINE LEARNING MODELS INCORPORATING HARDWARE AND RUNTIME ATTRIBUTES

NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES

MITIGATION OF CONTROL SET PACKING RESTRICTIONS FOR INTEGRATED CIRCUITS

SYSTEMS AND METHODS FOR PARALLELIZATION OF EMBEDDING OPERATIONS

SIMULATING DATA TRANSFERS FOR HIGH-LEVEL SYNTHESIS DESIGNS

AREA OPTIMIZED MEMORY IMPLEMENTATION USING DEDICATED MEMORY PRIMITIVES

SYSTEMS AND METHODS FOR TASK MANAGEMENT

APPARATUS AND METHOD OF PRINTING SOLDER ON PRINTED CIRCUIT BOARD FOR WARPAGE COMPENSATION

SYSTEMS AND METHODS FOR HARDWARE MESSAGE PROCESSING

INDUCTOR CIRCUITRY

CO-SIMULATION ON A SYSTEM-ON-CHIP

EXTENDING SYNCHRONOUS CIRCUIT DESIGNS OVER ASYNCHRONOUS COMMUNICATION LINKS UTILIZING A TRANSACTOR-BASED FRAMEWORK

DEVICES, SYSTEMS, AND METHODS FOR A PROGRAMMABLE THREE-DIMENSIONAL SEMICONDUCTOR POWER DELIVERY NETWORK

SCHEDULING KERNELS ON A DATA PROCESSING SYSTEM WITH ONE OR MORE COMPUTE CIRCUITS

CONTROL SET OPTIMIZATION FOR CIRCUIT DESIGNS BY DETECTION OF REGISTERS WITH REDUNDANT RESETS

LOW-SKEW SOLUTIONS FOR LOCAL CLOCK NETS IN INTEGRATED CIRCUITS