XILINX, INC.

Drift-Based Margin Optimizer

In-Situ Electrical Connectivity Detection

FINE-GRAINED PREEMPTION OF A DATA FLOW ARCHITECTURE BASED NEURAL PROCESSING UNIT

OPTICAL COUPLER FOR PHOTONIC INTEGRATED CIRCUITS

COMMAND STREAM STITCHING FOR HARDWARE ACCELERATION

SYSTEMS AND METHODS FOR MANAGING ORDER OF COMMAND PROCESSING

CASCADED LOOKUP-TABLE MAPPING FOR CIRCUIT DESIGN AND IMPLEMENTATION

ACCELERATION OF CRYPTOGRAPHIC OPERATIONS

CONFIGURATION OF AN ADAPTIVE SYSTEM-ON-CHIP

CARRY CHAIN REDUCTION AND REPLACEMENT FOR CIRCUIT DESIGNS

OFFLOADING OPERATIONS USING A NETWORK INTERFACE CONTROLLER

Selectable Slice Mapping

CIRCUIT DESIGN IMPLEMENTATION FOR 3-DIMENSIONAL INTEGRATED CIRCUIT DEVICES

SYSTEMS AND METHODS FOR CARD RETENTION FEATURE RETROFIT

MEMORY DEFRAGMENTATION IN PROGRAMMABLE INTEGRATED CIRCUIT DEVICES

TRANSMISSION AND PROCESSING OF DATA IN PARALLEL SYSTEMS

TRANSMISSION AND PROCESSING OF DATA IN PARALLEL SYSTEMS

MACHINE LEARNING DEPLOYMENT PLATFORM

TRANSMISSION AND PROCESSING OF DATA IN PARALLEL SYSTEMS

SYSTEMS AND METHODS FOR PROVIDING POWER INTEGRITY TO FUNCTIONAL CIRCUITRY OF A SEMICONDUCTOR DEVICE

FIREWALLING COMMUNICATION PORTS IN A MULTI-PORT SYSTEM

3D INTEGRATED CIRCUIT WITH ENHANCED DEBUGGING CAPABILITY

REDUNDANT DATA STORAGE USING INCREMENTAL ERROR DETECTION WITH NON-ZERO SEEDS

SECURE READBACK FROM CONFIGURATION MEMORY

MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY

LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS TO MEMORY CONTROLLERS

PROGRAMMABLE CONGESTION MONITORING AND/OR CONTROL

EMULATING A CIRCUIT DESIGN IN COMMUNICATION WITH A PERIPHERAL

ON-SITE UPDATING OF MACHINE LEARNING MODELS AND MACHINE LEARNING MODELS INCORPORATING HARDWARE AND RUNTIME ATTRIBUTES

SYSTEMS AND METHODS FOR SCALABLE COMMUNICATIONS

NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES

MITIGATION OF CONTROL SET PACKING RESTRICTIONS FOR INTEGRATED CIRCUITS

SYSTEMS AND METHODS FOR PARALLELIZATION OF EMBEDDING OPERATIONS

SIMULATING DATA TRANSFERS FOR HIGH-LEVEL SYNTHESIS DESIGNS

PROTECTION OF A CIRCUIT DESIGN WITHIN A DESIGN CONTAINER

AREA OPTIMIZED MEMORY IMPLEMENTATION USING DEDICATED MEMORY PRIMITIVES

SYSTEMS AND METHODS FOR TASK MANAGEMENT

APPARATUS AND METHOD OF PRINTING SOLDER ON PRINTED CIRCUIT BOARD FOR WARPAGE COMPENSATION

SYSTEMS AND METHODS FOR HARDWARE MESSAGE PROCESSING

INDUCTOR CIRCUITRY

CO-SIMULATION ON A SYSTEM-ON-CHIP

EXTENDING SYNCHRONOUS CIRCUIT DESIGNS OVER ASYNCHRONOUS COMMUNICATION LINKS UTILIZING A TRANSACTOR-BASED FRAMEWORK

DEVICES, SYSTEMS, AND METHODS FOR A PROGRAMMABLE THREE-DIMENSIONAL SEMICONDUCTOR POWER DELIVERY NETWORK

SCHEDULING KERNELS ON A DATA PROCESSING SYSTEM WITH ONE OR MORE COMPUTE CIRCUITS

CONTROL SET OPTIMIZATION FOR CIRCUIT DESIGNS BY DETECTION OF REGISTERS WITH REDUNDANT RESETS

LOW-SKEW SOLUTIONS FOR LOCAL CLOCK NETS IN INTEGRATED CIRCUITS

SYSTEMS AND METHODS FOR MACHINE LEARNING BASED VOLTAGE DROP PREDICTION FOR A 3D STACKED DEVICE

SMART PREDICTOR CIRCUITRY INSERTION BASED ON STRUCTURAL ANALYSIS AND SWITCHING ACTIVITY

COMPILING A TENSOR TILING SPECIFICATION TO MULTI-DIMENSIONAL DATA MOVER CIRCUIT CONFIGURATIONS

TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY

MULTI-HOST AND MULTI-CLIENT DIRECT MEMORY ACCESS SYSTEM HAVING A READ SCHEDULER

SYNTHESIS OF SIMULATION-DIRECTED STATEMENTS

PERFORMANCE EVALUATOR FOR A HETEROGENOUS HARDWARE PLATFORM

HIGH-LEVEL SYNTHESIS OF DESIGNS USING LOOP-AWARE EXECUTION INFORMATION

SELF-AUTHENTICATION OF DATA STORED OFF-CHIP