Allen, Texas
United States
32
2020-10-22
The entities that hold a legal rights for patent applications filed by inventor Lee Seok-Jun:
Seok-Jun Lee from Allen, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Low energy accelerator processor architecture with short parallel instruction word
#2 | 2020-06-11Apparatus and method for operating multiple cameras for digital photography
#3 | 2020-01-23System and method for 3D association of detected objects
#4 | 2019-12-05Methods and instructions for a 32-bit arithmetic support using 16-bit multiply and 32-bit addition
#5 | 2019-11-14Foveated domain storage and processing
#6 | 2019-11-14Method of analyzing objects in images recorded by a camera of a head mounted device
#7 | 2019-08-08Dynamic memory mapping for neural networks
#8 | 2019-02-28Electronic devices for and methods of implementing memory transfers for image warping in an electronic device
#9 | 2018-08-02Low energy accelerator processor architecture
#10 | 2018-01-18Low energy accelerator processor architecture with short parallel instruction word
#11 | 2017-09-07Hardware architecture for acceleration of computer vision and imaging processing
#12 | 2017-07-06Methods and instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition
#13 | 2017-05-25Computer and methods for solving math functions
#14 | 2017-03-02Load store circuit with dedicated single or dual bit shift circuit and opcodes for low power accelerator processor
#15 | 2016-10-06Low energy accelerator processor architecture with short parallel instruction word
#16 | 2016-10-06Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file
#17 | 2016-07-07Method and apparatus for a wearable based authentication for improved user experience
#18 | 2015-05-07PROCESSOR TRIGONOMETRIC COMPUTATION
#19 | 2015-04-30Computer and methods for solving math functions
#20 | 2011-03-03Method, device, and digital circuitry for providing a closed-form solution to a scaled error locator polynomial used in BCH decoding
#21 | 2011-03-03Receiver power saving via block code failure detection
#22 | 2010-02-11Low-power predecoding based viterbi decoding
#23 | 2010-02-11Reduced complexity viterbi decoding
#24 | 2010-02-11Sharing logic circuitry for a maximum likelihood MIMO decoder and a viterbi decoder
#25 | 2009-12-17DIRECT MEMORY ACCESS CHANNEL
#26 | 2009-11-05System and method for time domain interpolation of signals for channel estimation
#27 | 2009-04-30Reduced complexity Viterbi decoder
#28 | 2009-04-02High-speed add-compare-select (ACS) circuit
#29 | 2008-12-04N-CANDIDATE DEPTH-FIRST DECODING
#30 | 2008-12-04Scalable VLSI architecture for K-best breadth-first decoding
#31 | 2007-06-21De-interleaver synchronization methods and apparatus
#32 | 2007-05-17CASCADED RADIX ARCHITECTURE FOR HIGH-SPEED VITERBI DECODER
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