Inventor profile of:

Hideki Takeuchi

City:

Austin, Texas

Country:

United States

Published Applications:

12

Last publication date:

2018-02-08

Top Assignees for applications by Hideki Takeuchi

The entities that hold a legal rights for patent applications filed by inventor Takeuchi Hideki:

Recent patent applications by Takeuchi Hideki

Hideki Takeuchi from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-02-08
US20180040743A1
Electricity

Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers

#2 | 2018-02-08
US20180040725A1
Electricity

Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice

#3 | 2018-02-08
US20180040724A1
Electricity

Semiconductor device including resonant tunneling diode structure having a superlattice

#4 | 2018-02-08
US20180040714A1
Electricity

Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers

#5 | 2017-10-19
US20170301757A1
Electricity

Semiconductor device including a superlattice and replacement metal gate structure and related methods

#6 | 2016-11-17
US20160336407A1
Electricity

Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods

#7 | 2016-11-17
US20160336406A1
Electricity

Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods

#8 | 2016-05-26
US20160149023A1
Electricity

Semiconductor device including a superlattice and replacement metal gate structure and related methods

#9 | 2016-04-07
US20160099317A1
Electricity

Vertical semiconductor devices including superlattice punch through stop layer and related methods

#10 | 2015-05-28
US20150144878A1
Electricity

Semiconductor devices including superlattice depletion layer stack and related methods

#11 | 2015-05-28
US20150144877A1
Electricity

Vertical semiconductor devices including superlattice punch through stop layer and related methods

#12 | 2012-07-05
US20120171798A1
Performing operations; transporting

Damascene process for use in fabricating semiconductor structures having micro/nano gaps

InventorID:

1172988 ⎘