Los Gatos, California
United States
114
2025-07-03
111
2025-05-20
These are the the leading inventors for applications assigned to ATOMERA INCORPORATED:
ATOMERA INCORPORATED based in Los Gatos, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Integrated Circuit Chip Including Arrays Of Multi-Threaded Dynamic Random Access Memory Unit Cells
#2 | 2025-07-03Interconnect Structure For An Array Of Multi-Threaded Dynamic Random Access Memory Systems
#3 | 2025-04-17Single-Ended Sense Amplifiers And Methods For Operating Same
#4 | 2025-01-09 ✅ Patent 12,308,229 granted on 2025-05-20Method for making memory device including a superlattice gettering layer
#5 | 2024-11-14 ✅ Patent 12,382,689 granted on 2025-08-05METHOD FOR MAKING DMOS DEVICES INCLUDING A SUPERLATTICE AND FIELD PLATE FOR DRIFT REGION DIFFUSION
#6 | 2024-10-10 ✅ Patent 12,322,594 granted on 2025-06-03Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
#7 | 2024-09-26 ✅ Patent 12,230,694 granted on 2025-02-18Method for making nanostructure transistors with source/drain trench contact liners
#8 | 2024-09-26 ✅ Patent 12,142,669 granted on 2024-11-12Method for making nanostructure transistors with flush source/drain dopant blocking structures including a superlattice
#9 | 2024-09-26 ✅ Patent 12,142,662 granted on 2024-11-12Method for making nanostructure transistors with offset source/drain dopant blocking structures including a superlattice
#10 | 2024-09-26 ✅ Patent 12,417,912 granted on 2025-09-16RADIO FREQUENCY (RF) SEMICONDUCTOR DEVICES INCLUDING A GROUND PLANE LAYER HAVING A SUPERLATTICE
#11 | 2024-09-19 ✅ Patent 12,315,722 granted on 2025-05-27Method for making a radio frequency silicon-on-insulator (RFSOI) wafer including a superlattice
#12 | 2024-07-25 ✅ Patent 12,635,155 granted on 2026-05-19METHODS FOR MAKING BIPOLAR JUNCTION TRANSISTORS INCLUDING EMITTER-BASE AND BASE-COLLECTOR SUPERLATTICES
#13 | 2024-06-13 ✅ Patent 12,315,723 granted on 2025-05-27Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
#14 | 2024-05-23 ✅ Patent 12,477,798 granted on 2025-11-18SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ENRICHED SILICON 28 EPITAXIAL LAYER
#15 | 2024-05-16 ✅ Patent 12,635,122 granted on 2026-05-19Multi-Chip Memory System Including DRAM Chips With Integrated Comparator Arrays And Method Of Operating Same
#16 | 2024-03-21 ✅ Patent 12,199,180 granted on 2025-01-14Semiconductor device including a superlattice and an asymmetric channel and related methods
#17 | 2024-03-21 ✅ Patent 12,439,618 granted on 2025-10-07BIPOLAR JUNCTION TRANSISTORS INCLUDING EMITTER-BASE AND BASE-COLLECTOR SUPERLATTICES
#18 | 2024-02-29 ✅ Patent 12,635,271 granted on 2026-05-19METHOD FOR MAKING IMAGE SENSOR DEVICES INCLUDING A SUPERLATTICE
#19 | 2024-02-29 ✅ Patent 12,575,199 granted on 2026-03-10IMAGE SENSOR DEVICES INCLUDING A SUPERLATTICE
#20 | 2024-02-22 ✅ Patent 12,119,380 granted on 2024-10-15Method for making semiconductor device including superlattice with oxygen and carbon monolayers
#21 | 2023-12-07 ✅ Patent 12,046,470 granted on 2024-07-23Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
#22 | 2023-11-09 ✅ Patent 12,267,996 granted on 2025-04-01DRAM sense amplifier architecture with reduced power consumption and related methods
#23 | 2023-11-09 ✅ Patent 12,199,148 granted on 2025-01-14Semiconductor device including superlattice with O18 enriched monolayers
#24 | 2023-11-02 ✅ Patent 12,014,923 granted on 2024-06-18Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
#25 | 2023-05-04 ✅ Patent 11,721,546 granted on 2023-08-08Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
#26 | 2023-05-04 ✅ Patent 11,631,584 granted on 2023-04-18Method for making semiconductor device with selective etching of superlattice to define etch stop layer
#27 | 2023-04-20 ✅ Patent 12,142,641 granted on 2024-11-12Method for making gate-all-around (GAA) device including a superlattice
#28 | 2023-04-20 ✅ Patent 11,978,771 granted on 2024-05-07Gate-all-around (GAA) device including a superlattice
#29 | 2022-12-01 ✅ Patent 11,682,712 granted on 2023-06-20Method for making semiconductor device including superlattice with O18 enriched monolayers
#30 | 2022-12-01 ✅ Patent 11,728,385 granted on 2023-08-15Semiconductor device including superlattice with Oenriched monolayers
#31 | 2022-11-24 ✅ Patent 12,439,658 granted on 2025-10-07SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE PROVIDING METAL WORK FUNCTION TUNING
#32 | 2022-11-17 ✅ Patent 11,923,431 granted on 2024-03-05Bipolar junction transistors including emitter-base and base-collector superlattices
#33 | 2022-11-17 ✅ Patent 11,935,940 granted on 2024-03-19Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
#34 | 2022-11-03 ✅ Patent 11,923,418 granted on 2024-03-05Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
#35 | 2022-10-27 ✅ Patent 11,810,784 granted on 2023-11-07Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
#36 | 2022-09-08 ✅ Patent 11,664,427 granted on 2023-05-30Vertical semiconductor device with enhanced contact structure and associated methods
#37 | 2022-09-08 ✅ Patent 11,742,202 granted on 2023-08-29Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
#38 | 2022-09-08 ✅ Patent 12,020,926 granted on 2024-06-25Radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
#39 | 2022-07-28 ✅ Patent 11,869,968 granted on 2024-01-09Semiconductor device including a superlattice and an asymmetric channel and related methods
#40 | 2022-01-06 ✅ Patent 11,848,356 granted on 2023-12-19Method for making semiconductor device including superlattice with oxygen and carbon monolayers
#41 | 2022-01-06 ✅ Patent 11,837,634 granted on 2023-12-05Semiconductor device including superlattice with oxygen and carbon monolayers
#42 | 2022-01-06 ✅ Patent 12,191,160 granted on 2025-01-07Method for making a semiconductor superlattices with different non-semiconductor thermal stabilities
#43 | 2021-12-16 ✅ Patent 11,569,368 granted on 2023-01-31Method for making semiconductor device including a superlattice and providing reduced gate leakage
#44 | 2021-12-16 ✅ Patent 11,469,302 granted on 2022-10-11Semiconductor device including a superlattice and providing reduced gate leakage
#45 | 2021-08-26 ✅ Patent 11,302,823 granted on 2022-04-12Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers
#46 | 2021-08-26 ✅ Patent 11,177,351 granted on 2021-11-16Semiconductor device including a superlattice with different non-semiconductor material monolayers
#47 | 2021-07-27 ✅ Patent 11,075,078 granted on 2021-07-27Method for making a semiconductor device including a superlattice within a recessed etch
#48 | 2021-07-15 ✅ Patent 11,437,487 granted on 2022-09-06Bipolar junction transistors including emitter-base and base-collector superlattices
#49 | 2021-07-15 ✅ Patent 11,437,486 granted on 2022-09-06Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
#50 | 2021-03-11 ✅ Patent 11,387,325 granted on 2022-07-12Vertical semiconductor device with enhanced contact structure and associated methods
#51 | 2021-01-21 ✅ Patent 10,937,888 granted on 2021-03-02Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices
#52 | 2021-01-21 ✅ Patent 10,937,868 granted on 2021-03-02Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices
#53 | 2021-01-21 ✅ Patent 11,183,565 granted on 2021-11-23Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods
#54 | 2021-01-21 ✅ Patent 10,879,357 granted on 2020-12-29Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice
#55 | 2020-12-31 ✅ Patent 11,430,869 granted on 2022-08-30Method for making superlattice structures with reduced defect densities
#56 | 2020-12-15 ✅ Patent 10,868,120 granted on 2020-12-15Method for making a varactor with hyper-abrupt junction region including a superlattice
#57 | 2020-11-17 ✅ Patent 10,840,388 granted on 2020-11-17Varactor with hyper-abrupt junction region including a superlattice
#58 | 2020-11-03 ✅ Patent 10,825,901 granted on 2020-11-03Semiconductor devices including hyper-abrupt junction region including a superlattice
#59 | 2020-11-03 ✅ Patent 10,825,902 granted on 2020-11-03Varactor with hyper-abrupt junction region including spaced-apart superlattices
#60 | 2020-10-29 ✅ Patent 11,329,154 granted on 2022-05-10Semiconductor device including a superlattice and an asymmetric channel and related methods
#61 | 2020-10-29 ✅ Patent 11,094,818 granted on 2021-08-17Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods
#62 | 2020-05-21 ✅ Patent 10,847,618 granted on 2020-11-24Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance
#63 | 2020-05-21 ✅ Patent 10,818,755 granted on 2020-10-27Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
#64 | 2020-05-21 ✅ Patent 10,854,717 granted on 2020-12-01Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
#65 | 2020-05-21 ✅ Patent 10,840,337 granted on 2020-11-17Method for making a FINFET having reduced contact resistance
#66 | 2020-05-21 ✅ Patent 10,840,336 granted on 2020-11-17Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
#67 | 2020-05-21 ✅ Patent 10,840,335 granted on 2020-11-17Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
#68 | 2020-03-17 ✅ Patent 10,593,761 granted on 2020-03-17Method for making a semiconductor device having reduced contact resistance
#69 | 2020-03-05 ✅ Patent 10,811,498 granted on 2020-10-20Method for making superlattice structures with reduced defect densities
#70 | 2020-03-05 ✅ Patent 10,566,191 granted on 2020-02-18Semiconductor device including superlattice structures with reduced defect densities
#71 | 2020-03-03 ✅ Patent 10,580,866 granted on 2020-03-03Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
#72 | 2020-03-03 ✅ Patent 10,580,867 granted on 2020-03-03FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
#73 | 2019-10-17 ✅ Patent 11,355,667 granted on 2022-06-07Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice
#74 | 2019-10-17 ✅ Patent 10,763,370 granted on 2020-09-01Inverted T channel field effect transistor (ITFET) including a superlattice
#75 | 2019-10-17 ✅ Patent 11,664,459 granted on 2023-05-30Method for making an inverted T channel field effect transistor (ITFET) including a superlattice
#76 | 2019-10-17 ✅ Patent 10,884,185 granted on 2021-01-05Semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice
#77 | 2019-09-12 ✅ Patent 10,777,451 granted on 2020-09-15Semiconductor device including enhanced contact structures having a superlattice
#78 | 2019-09-12 ✅ Patent 10,879,356 granted on 2020-12-29Method for making a semiconductor device including enhanced contact structures having a superlattice
#79 | 2019-09-12 ✅ Patent 10,727,049 granted on 2020-07-28Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
#80 | 2019-09-12 ✅ Patent 10,468,245 granted on 2019-11-05Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
#81 | 2019-06-20 ✅ Patent 10,355,151 granted on 2019-07-16CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
#82 | 2019-06-20 ✅ Patent 10,396,223 granted on 2019-08-27Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk
#83 | 2019-06-20 ✅ Patent 10,361,243 granted on 2019-07-23Method for making CMOS image sensor including superlattice to enhance infrared light absorption
#84 | 2019-06-20 ✅ Patent 10,461,118 granted on 2019-10-29Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
#85 | 2019-06-20 ✅ Patent 10,529,768 granted on 2020-01-07Method for making CMOS image sensor including pixels with read circuitry having a superlattice
#86 | 2019-06-20 ✅ Patent 10,367,028 granted on 2019-07-30CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
#87 | 2019-06-20 ✅ Patent 10,615,209 granted on 2020-04-07CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
#88 | 2019-06-20 ✅ Patent 10,529,757 granted on 2020-01-07CMOS image sensor including pixels with read circuitry having a superlattice
#89 | 2019-06-20 ✅ Patent 10,608,027 granted on 2020-03-31Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
#90 | 2019-06-20 ✅ Patent 10,304,881 granted on 2019-05-28CMOS image sensor with buried superlattice layer to reduce crosstalk
#91 | 2019-04-30 ✅ Patent 10,211,251 granted on 2019-02-19CMOS image sensor including superlattice to enhance infrared light absorption
#92 | 2019-02-21 ✅ Patent 10,741,436 granted on 2020-08-11Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface
#93 | 2018-12-13 ✅ Patent 10,367,064 granted on 2019-07-30Semiconductor device with recessed channel array transistor (RCAT) including a superlattice
#94 | 2018-12-13 ✅ Patent 10,636,879 granted on 2020-04-28Method for making DRAM with recessed channel array transistor (RCAT) including a superlattice
#95 | 2018-11-22 ✅ Patent 10,381,242 granted on 2019-08-13Method for making a semiconductor device including a superlattice as a gettering layer
#96 | 2018-11-22 ✅ Patent 10,410,880 granted on 2019-09-10Semiconductor device including a superlattice as a gettering layer
#97 | 2018-10-23 ✅ Patent 10,109,479 granted on 2018-10-23Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
#98 | 2018-02-22 ✅ Patent 10,191,105 granted on 2019-01-29Method for making a semiconductor device including threshold voltage measurement circuitry
#99 | 2018-02-22 ✅ Patent 10,107,854 granted on 2018-10-23Semiconductor device including threshold voltage measurement circuitry
#100 | 2018-02-08 ✅ Patent 10,170,603 granted on 2019-01-01Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers
Also check out Atomera Incorporated's (Los Gatos, United States) applicant profile with 166 patent applications submitted.
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