Folsom, California
United States
83
2023-03-30
The entities that hold a legal rights for patent applications filed by inventor Sethi Prashant:
Prashant Sethi from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:
HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES
#2 | 2022-10-20Flattening portal bridge
#3 | 2022-03-10TECHNOLOGIES FOR SCHEDULING ACCELERATION OF FUNCTIONS IN A POOL OF ACCELERATOR DEVICES
#4 | 2021-12-30Apparatuses, methods, and systems for instructions for operating system transparent instruction state management of new instructions for application threads
#5 | 2021-10-14ENHANCED DIRECTED SYSTEM MANAGEMENT INTERRUPT MECHANISM
#6 | 2021-07-29Flattening portal bridge
#7 | 2019-10-17Automatic switching and deployment of software or firmware based USB4 connection managers
#8 | 2019-04-18System and methods exchanging data between processors through concurrent shared memory
#9 | 2019-02-28USB-C multiple connector support for host and device mode configurations
#10 | 2019-02-14TECHNOLOGIES FOR SCHEDULING ACCELERATION OF FUNCTIONS IN A POOL OF ACCELERATOR DEVICES
#11 | 2018-11-15RECONFIGURABLE DEVICE MANAGER
#12 | 2018-09-06System and methods exchanging data between processors through concurrent shared memory
#13 | 2018-06-28Techniques for dynamically modifying platform form factors of a mobile device
#14 | 2018-05-17Bus-device-function address space mapping
#15 | 2018-04-05System and method for coupling a host device to secure and non-secure devices
#16 | 2018-03-22USB-C multiple connector support for host and device mode configurations
#17 | 2018-02-15Multimodal interface
#18 | 2018-01-11Restricted address translation to protect against device-TLB vulnerabilities
#19 | 2017-10-05Enhanced directed system management interrupt mechanism
#20 | 2017-09-07Flattening portal bridge
#21 | 2017-07-13Address translation for scalable virtualization of input/output devices
#22 | 2017-06-29Speculative enumeration of bus-device-function address space
#23 | 2017-05-25System and methods exchanging data between processors through concurrent shared memory
#24 | 2017-04-13Apparatus, system, and method for persistent user-level thread
#25 | 2017-01-12MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY OF INSTRUCTION SEQUENCERS
#26 | 2016-09-22Apparatus, system, and method for persistent user-level thread
#27 | 2016-06-30System and methods exchanging data between processors through concurrent shared memory
#28 | 2016-01-21Mechanism for instruction set based thread execution on a plurality of instruction sequencers
#29 | 2015-06-11Transaction layer packet formatting
#30 | 2015-05-28PCI express transaction descriptor
#31 | 2014-07-24Providing hardware support for shared virtual memory between local and remote physical memory
#32 | 2014-04-24Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
#33 | 2014-03-13Systems and methods exchanging data between processors through concurrent shared memory
#34 | 2013-10-17Apparatus, system, and method for persistent user-level thread
#35 | 2013-09-19Instruction for enabling a processor wait state
#36 | 2013-08-22Mechanism for instruction set based thread execution of a plurality of instruction sequencers
#37 | 2013-07-18Instruction for enabling a processor wait state
#38 | 2013-05-23PCI EXPRESS ENHANCEMENTS AND EXTENSIONS
#39 | 2013-05-23PCI EXPRESS ENHANCEMENTS AND EXTENSIONS
#40 | 2013-05-23Prefectching in PCI express
#41 | 2013-05-02Atomic operations in PCI express
#42 | 2013-04-18Transaction re-ordering
#43 | 2013-04-11PCI EXPRESS ENHANCEMENTS AND EXTENSIONS
#44 | 2013-02-28Mechanism for instruction set based thread execution on a plurality of instruction sequencers
#45 | 2012-10-04Atomic operations
#46 | 2012-04-12PCI express enhancements and extensions
#47 | 2012-02-09PCI express enhancements and extensions including device window caching
#48 | 2012-01-19Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
#49 | 2011-12-22Apparatus, system, and method for persistent user-level thread
#50 | 2011-09-29PCI express enhancements and extensions
#51 | 2011-08-25PCI express enhancements and extensions
#52 | 2011-07-14PCI express enhancements and extensions including transactions having prefetch parameters
#53 | 2011-06-30PCI express enhancements and extensions
#54 | 2011-06-23Instruction for enabling a processor wait state
#55 | 2011-03-24Providing hardware support for shared virtual memory between local and remote physical memory
#56 | 2011-03-24PCI express enhancements and extensions
#57 | 2010-07-08Systems and methods exchanging data between processors through concurrent shared memory
#58 | 2008-09-04PCI express enhancements and extensions
#59 | 2008-08-14PCI EXPRESS ENHANCEMENTS AND EXTENSIONS
#60 | 2008-08-14PCI express enhancements and extensions
#61 | 2008-08-14PCI express enhancements and extensions
#62 | 2008-07-03Low latency mechanism for data transfers between a media controller and a communication device
#63 | 2008-05-08PCI express enhancements and extensions
#64 | 2007-06-12General input/output architecture, protocol and related methods to support legacy interrupts
#65 | 2007-04-05Apparatus, system, and method for persistent user-level thread
#66 | 2007-01-04Mechanism for instruction set based thread execution on a plurality of instruction sequencers
#67 | 2006-12-14Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
#68 | 2006-11-30Transparent support for operating system services for a sequestered sequencer
#69 | 2006-10-10System and method for communicating over intra-hierarchy and inter-hierarchy links
#70 | 2006-10-05Sequencer address management
#71 | 2006-07-06Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
#72 | 2006-07-06Mechanism to emulate user-level multithreading on an OS-sequestered sequencer
#73 | 2006-06-29Mechanism for processing uncacheable streaming data
#74 | 2006-06-22Media memory system and method for providing concurrent memory access to a plurality of processors through separate translation table information
#75 | 2006-06-20Method and apparatus for in-band signaling of runtime general purpose events
#76 | 2006-04-25Device virtualization and assignment of interconnect devices
#77 | 2005-12-29Circuitry to selectively produce MSI signals
#78 | 2005-11-24I/O configuration messaging within a link-based computing system
#79 | 2005-10-13Sharing of interrupts between operating entities
#80 | 2005-09-22Method and system for configuration of processor integrated devices in multi-processor systems
#81 | 2005-08-18System including real-time data communication features
#82 | 2005-06-14Mapping of interconnect configuration space
#83 | 2005-03-08System including real-time data communication features
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