Stijn Eyerman

DATA PREFETCHING BASED ON BOTH INTRA-TILE AND INTER-TILE STRIDE INFORMATION

APPARATUS AND METHOD FOR MANAGING MEMORY PAGES, AND NON- TRANSITORY COMPUTER-READABLE MEDIUM

SPECULATIVE INVOCATION OF ACCELERATORS IN OUT-OF-ORDER PIPELINES

UNIFIED TRANSFER ENGINE FOR COMPUTE ACCELERATORS

DATA ACCESS PATTERN PROFILER FOR MEMORY COMPRESSION SCHEME SELECTION

VARIABLE CHUNK SIZE MEMORY COMPRESSION

DELAYED CACHE WRITEBACK INSTRUCTIONS FOR IMPROVED DATA SHARING IN MANYCORE PROCESSORS

OS-TRANSPARENT MEMORY DECOMPRESSION WITH HARDWARE ACCELERATION

METHOD AND APPARATUS FOR PARTIAL VIRTUALIZATION IN A PROCESSOR

AUTOMATIC FUSION OF ARITHMETIC IN-FLIGHT INSTRUCTIONS

VISUALIZING MEMORY BANDWIDTH UTILIZATION USING MEMORY BANDWIDTH STACK

PERFORMANCE MODELING OF GRAPH PROCESSING COMPUTING ARCHITECTURES

Instruction and logic for code prefetching

DELAYED CACHE WRITEBACK INSTRUCTIONS FOR IMPROVED DATA SHARING IN MANYCORE PROCESSORS

Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics

System, apparatus and method for dynamic automatic sub-cacheline granularity memory access control

Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics

Indirect memory fetcher

Independent tuning of multiple hardware prefetchers

Storage architectures for graph analysis applications

TECHNOLOGIES FOR PROCESSOR SIMULATION MODELING WITH MACHINE LEARNING

Instruction window centric processor simulation

Counter architecture for online DVFS profitability estimation

METHODS AND SYSTEMS FOR SIMULATING A PROCESSOR