Rwik Sengupta

Context-aware circuit design layout construct

Electronic design tracing and tamper detection using automatically generated layout patterns

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

System and method for device placement

VFET standard cell architecture with improved contact and super via

System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs)

VFET standard cell architecture with improved contact and super via

Apparatus and method of forming backside buried conductor in integrated circuit

Variation resistant 3T3R binary weight cell with low output current and high on/off ratio

4T4R ternary weight cell with high on/off ratio background

2T2R binary weight cell with high on/off ratio background

METHOD OF DESIGNING A LAYOUT FOR A SEMICONDUCTOR INTEGRATED CIRCUIT

Nanosheet field effect transistor cell architecture

Semiconductor device and method for making the same

Method and system for providing a reverse engineering resistant hardware embedded security module

Dielectric separation of partial GAA FETs

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

Method and system for providing a reverse-engineering resistant hardware embedded security module

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Power rail for standard cell block

Unipolar complementary logic

Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating

Method for forming low parasitic capacitance source and drain contacts

Stacked independently contacted field effect transistor having electrically separated first and second gates

Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures

Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same

Semiconductor device having buried power rail

Metal oxysilicate diffusion barriers for damascene metallization with low RC delays and methods for forming the same

MULTIPLE CPP FOR INCREASED SOURCE/DRAIN AREA FOR FETS INCLUDING IN A CRITICAL SPEED PATH

Methods of forming semiconductor devices including conductive contacts on source/drains

Semiconductor device with an isolation gate and method of forming

Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width

Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same

Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators

Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same