Thomas M. Shaw

Compressive zone to reduce dicing defects

Step pyramid shaped structure to reduce dicing defects

Techniques to improve reliability in Cu interconnects using Cu intermetallics

Techniques to improve reliability in Cu interconnects using Cu intermetallics

Strain monitoring of MRAM arrays

Strain monitoring of MRAM arrays

Techniques to improve reliability in Cu interconnects using Cu intermetallics

Integrated time dependent dielectric breakdown reliability testing

Piezoelectronic switch device for RF applications

Integrated time dependent dielectric breakdown reliability testing

Piezoelectronic switch device for RF applications

Controlling fragmentation of chemically strengthened glass

Controlling fragmentation of chemically strengthened glass

Piezoelectronic switch device for RF applications

Volumetric integrated circuit and volumetric integrated circuit manufacturing method

Method and structure for determining thermal cycle reliability

Semiconductor article having a zig-zag guard ring and method of forming the same

Semiconductor test and monitoring structure to detect boundaries of safe effective modulus

Structure and method for making crack stop for 3D integrated circuits

DIELETRIC CAP HAVING MATERIAL WITH OPTICAL BAND GAP TO SUBSTANTIALLY BLOCK UV RADIATION DURING CURING TREATMENT, AND RELATED METHODS

Integrated time dependent dielectric breakdown reliability testing

SEMICONDUCTOR STRUCTURE

Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections

SEMICONDUCTOR STRUCTURE

Integrated time dependent dielectric breakdown reliability testing

Semiconductor test and monitoring structure to detect boundaries of safe effective modulus

Hybrid interconnect structure for performance improvement and reliability enhancement

Hybrid interconnect structure for performance improvement and reliability enhancement

Hybrid interconnect structure for performance improvement and reliability enhancement

Multiple step anneal method and semiconductor formed by multiple step anneal

Method of making a copper interconnect having a barrier liner of multiple metal layers

Low k porous SiCOH dielectric and integration with post film formation treatment

Redundant metal barrier structure for interconnect applications

Hybrid interconnect structure for performance improvement and reliability enhancement

Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

Device and methodology for reducing effective dielectric constant in semiconductor devices

Redundant metal barrier structure for interconnect applications

BARRIER SEQUENCE FOR USE IN COPPER INTERCONNECT METALLIZATION

LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT

LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT

Method of forming crack trapping and arrest in thin film structures

Strengthening of a structure by infiltration

Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

Reducing effective dielectric constant in semiconductor devices

Method and structure for determining thermal cycle reliability

BEOL interconnect structures with improved resistance to stress

Hybrid interconnect structure for performance improvement and reliability enhancement

DIELECTRIC CAP HAVING MATERIAL WITH OPTICAL BAND GAP TO SUBSTANTIALLY BLOCK UV RADIATION DURING CURING TREATMENT, AND RELATED METHODS

Hardmask for improved reliability of silicon based dielectrics

HARDMASK FOR IMPROVED RELIABILITY OF SILICON BASED DIELECTRICS

Device and methodology for reducing effective dielectric constant in semiconductor devices

Device and methodology for reducing effective dielectric constant in semiconductor devices

Process for interfacial adhesion in laminate structures through patterned roughing of a surface

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Method for reducing film stress for SiCOH low-k dielectric materials

Structure for determining thermal cycle reliability

Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor

Building metal pillars in a chip for structure support

Hardmask for reliability of silicon based dielectrics

Control of liner thickness for improving thermal cycle reliability

Stacked via-stud with improved reliability in copper metallurgy

Reliability of low-k dielectric devices with energy dissipative layer

Process for interfacial adhesion in laminate structures through patterned roughing of a surface

Stacked via-stud with improved reliability in copper metallurgy

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Control of liner thickness for improving thermal cycle reliability

Crackstop with release layer for crack control in semiconductors

Method and structure for determining thermal cycle reliability

Device and methodology for reducing effective dielectric constant in semiconductor devices

Building metal pillars in a chip for structure support

Tuneable ferroelectric decoupling capacitor

Method of extracting properties of back end of line (BEOL) chip architecture