Schenectady, New York
United States
50
2026-06-18
The entities that hold a legal rights for patent applications filed by inventor Nguyen Son:
Son Nguyen from Schenectady, US has applied for patents for these inventions. The list has both pending applications and granted patents:
GRAPHENE CAP LAYER WITH COMPOSITE ETCH STOP LAYER
#2 | 2026-02-12DAMASCENE INTERCONNECTS WITH BILAYER LINER
#3 | 2025-12-11LOW-K DIELECTRIC MATERIAL FOR INTERCONNECT STRUCTURES
#4 | 2025-10-02DIRECTIONAL CONDUCTOR INTERCONNECT WITH EMBEDDED VIA
#5 | 2024-12-05METAL INTERCONNECT LAYERS FOR FET ARCHITECTURES
#6 | 2024-10-03HIGH DENSITY METAL-INSULATOR-METAL CAPACITOR
#7 | 2024-09-26ENCASPULATED MRAM DEVICE WITH WRAP-AROUND TOP ELECTRODE
#8 | 2024-09-19AIR GAP IN BEOL INTERCONNECT
#9 | 2024-07-04GRAPHENE COATED INTERCONNECTS WITH AIRGAP STRUCTURES
#10 | 2024-05-02STACKED FIELD EFFECT TRANSISTOR STRUCTURE WITH INDEPENDENT GATE CONTROL BETWEEN TOP AND BOTTOM GATES
#11 | 2024-04-04FIELD EFFECT TRANSISTOR WITH BACKSIDE SOURCE/DRAIN
#12 | 2024-04-04FIELD EFFECT TRANSISTOR WITH BACKSIDE SOURCE/DRAIN
#13 | 2024-03-28DIRECT BACKSIDE CONTACT WITH REPLACEMENT BACKSIDE DIELECTRIC
#14 | 2024-03-07BACKSIDE CONTACT THAT REDUCES RISK OF CONTACT TO GATE SHORT
#15 | 2023-07-27SELECTIVE DEPOSITION AND CROSS-LINKING OF POLYMERIC DIELECTRIC MATERIAL
#16 | 2023-06-22SELECTIVE DEPOSITION ENABLED BY VAPOR PHASE INHIBITOR
#17 | 2023-06-15DOPANT-FREE INHIBITOR FOR AREA SELECTIVE DEPOSITIONS
#18 | 2023-06-08Etch Back and Film Profile Shaping of Selective Dielectric Deposition
#19 | 2023-06-08SAM FORMULATIONS AND CLEANING TO PROMOTE QUICK DEPOSITIONS
#20 | 2023-05-18SELECTIVE DEPOSITION ON METALS USING POROUS LOW-K MATERIALS
#21 | 2023-05-11LEVELING DIELECTRIC SURFACES FOR CONTACT FORMATION WITH EMBEDDED MEMORY ARRAYS
#22 | 2023-04-06Composite interconnect formation using graphene
#23 | 2022-11-10Semiconductor structure having alternating selective metal and dielectric layers
#24 | 2021-10-07Selective deposition with SAM for fully aligned via
#25 | 2021-05-20Nano multilayer carbon-rich low-k spacer
#26 | 2021-04-01Metallic interconnect structure
#27 | 2020-09-15Semiconductor device with selective dielectric deposition
#28 | 2020-07-23Forming high carbon content flowable dielectric film with low processing damage
#29 | 2020-06-04Semiconductor structures of more uniform thickness
#30 | 2020-04-16Dielectric fill for memory pillar elements
#31 | 2020-04-09Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabrication
#32 | 2020-03-12Nano multilayer carbon-rich low-k spacer
#33 | 2020-02-27Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers
#34 | 2020-01-16Disposable laser/flash anneal absorber for embedded neuromorphic memory device fabrication
#35 | 2019-10-31Asymmetric air spacer gate-controlled device with reduced parasitic capacitance
#36 | 2019-10-31Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers
#37 | 2018-04-19Air gap and air spacer pinch off
#38 | 2018-03-29Air gap and air spacer pinch off
#39 | 2018-03-29Air gap and air spacer pinch off
#40 | 2018-03-29Air gap and air spacer pinch off
#41 | 2017-10-17Air gap and air spacer pinch off
#42 | 2017-10-10Air gap and air spacer pinch off
#43 | 2014-09-25Interlevel dielectric stack for interconnect structures
#44 | 2014-09-11Interlevel dielectric stack for interconnect structures
#45 | 2014-06-26Advanced low k cap film formation process for nano electronic devices
#46 | 2013-12-05Corrosion/etching protection in integration circuit fabrications
#47 | 2013-01-03Multilayered low k cap with conformal gap fill and UV stable compressive stress properties
#48 | 2012-08-09Advanced low k cap film formation process for nano electronic devices
#49 | 2012-08-02ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES
#50 | 2009-07-16Advanced low k cap film formation process for nano electronic devices
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