Applied Materials, Inc.

GATE ALL AROUND BACKSIDE POWER RAIL FORMATION WITH MULTI-COLOR BACKSIDE DIELECTRIC ISOLATION SCHEME

SURFACE CONDITIONING PROCESSES FOR SEMICONDUCTOR PROCESSING CHAMBER PARTS

Modifying Openings of an Extreme Ultraviolet Masking Layer

SYSTEM AND METHOD FOR RESONATOR TUNING USING VARIABLE CAPACITOR

SUBSTRATE PROPERTY CONTROL USING DOSE-DEPENDENT RESPONSE

SCANNED BEAM DOSE RATE MEASUREMENT FOR ION BEAM OPTIMIZATION

LINE CD MODULATION AND END-TO-END CD MANIPULATION WITH ANGLED ETCH & DEPOSITION

INTEGRATED WET CLEAN FOR BEVEL TREATMENTS

SUBSTRATE POLISHING HEAD FOR OPTICAL ENHANCEMENT ANALYSIS

MASK WRITING SYSTEM, BEAM SHAPING MODULE AND METHOD OF LASER BEAM PROCESSING

SELECTIVE ETCHING OF SILICON-CONTAINING MATERIAL RELATIVE TO METAL-DOPED BORON FILMS

ANGLED ION IMPLANT TO ENABLE VOID-FREE FILLING OF HIGH ASPECT RATIO TRENCH

CONFINED CHARGE TRAP LAYER

DRIFT TUBE ASSEMBLY FOR LINEAR ACCELERATORS

CARBON-DOPED PVD DEPOSITED COBALT LINER LAYER FOR IMPROVED CU REFLOW

INTEGRATED WET CLEAN FOR EPITAXIAL GROWTH

MULTI-COMPARTMENT GAS PANEL ASSEMBLY

REMOVING OR PREVENTING RESIDUE SUBSEQUENT TO REPAIRING LOW-K MATERIALS

SYSTEMS AND METHODS FOR DEPOSITION RESIDUE CONTROL

REPAIRING LOW-K MATERIALS WITH SILICON-FREE TREATMENT PRECURSORS TO PREVENT SILICON RESIDUE FORMATION

OXIDATION GROWTH MODULATION

DIRECT WORD LINE CONTACT AND METHODS OF MANUFACTURE FOR 3D MEMORY

BATCH PROCESSING CHAMBERS FOR PLASMA-ENHANCED DEPOSITION

BEAM CONDITIONING FOR DEFECT CONTROL IN BEAMLINE ION IMPLANTER

AMPOULE FOR A SEMICONDUCTOR MANUFACTURING PRECURSOR

METHODS OF SELECTIVELY ETCHING SILICON

METHODS OF DEPOSITING THERMALLY CONDUCTIVE POLYMERIC FILMS

STAGGERED BIT LINES FOR ADVANCED DRAM

WORD LINE CONTACT FOR 3D MEMORY

SYSTEM AND METHOD FOR HIGH ANGLE ION BEAM

OPTICAL INSPECTION OF WAFER BEVELS USING MULTIPLE LIGHT SOURCES

CONTROLLING ARCING WITH SEASON

Subtractive Metal flow with Tip-to-Tip Critical Dimension Reduction

DIRECTIONAL ANGLED ETCH FOR HARDMASK OPENING AND LWR IMPROVEMENT

METHODS OF IMPROVING EUV PATTERNING OF CONTACT HOLES AND VIAS BY ION IMPLANT AND DIRECTIONAL DEPOSITION

METHODS OF DEPOSITING REFLOWABLE POLYMER FILMS

SYSTEM FOR TARGET ARCING MAPPING AND PLASMA DIAGNOSIS

ENERGY MEASUREMENT SYSTEM AND METHOD OF ENERGY MEASUREMENT IN LINEAR ACCELERATOR

FAST BEAM CALIBRATION PROCEDURE FOR BEAMLINE ION IMPLANTER

LIFT PIN ASSEMBLY FOR SUBSTRATE PROCESSING CHAMBER

PROCESSING METHODS TO IMPROVE ETCHED SILICON-AND-GERMANIUM-CONTAINING MATERIAL SURFACE PROPERTIES

LARGE AREA GAPFILL USING VOLUMETRIC EXPANSION

POROSITY-FREE PHENOLIC EPOXIES

CONTROLLING AUTO-DOPING IN EPITAXIALLY GROWN SILICON-CONTAINING MATERIALS

NANOPILLAR STRUCTURE OF IMAGE SENSOR DEVICE AND METHOD OF FORMING

SHAPED ION BLOCKER PLATE FOR INDIRECT CCP

SHIELD FOR ENHANCED PRECURSOR PURGING

METHODS OF DEPOSITING METAL-CONTAINING FILMS HAVING A COMPOSITION GRADIENT

LOW RESISTIVITY METAL STACKS AND METHODS OF DEPOSITING THE SAME

BONDED DEVICE HAVING SPLIT BONDING LAYER AND METHODS OF FORMATION

METHODS OF DEPOSITING IRIDIUM-CONTAINING FILMS FOR MICROELECTRONIC DEVICES

CYCLIC ETCH OF SILICON OXIDE AND POLYSILICON

COMBINED THERMAL AND PLASMA ASSISTED ATOMIC LAYER DEPOSITION

PRECURSOR DELIVERY SYSTEM

MULTIPLE PORT GAS INJECTION AND EXHAUST FOR BATCH SUBSTRATE PROCESSING CHAMBER

MODULAR MULTI-DIRECTIONAL GAS MIXING BLOCK

METHOD AND MATERIAL SYSTEM FOR MULTI-THRESHOLD-VOLTAGE GATES IN SEMICONDUCTOR STRUCTURES

GREYSCALE LITHOGRAPHY FOR SUBSTRATE TOPOGRAPHY CORRECTION

GATE-ALL-AROUND TRANSISTORS AND METHODS OF FORMING

ION IMPLANTER, CONTROL SYSTEM, AND TECHNIQUES FOR TUNING BUNCHER OF ION IMPLANTER

VARIABLE CONDUCTANCE EDGE RING FOR VAPOR DEPOSITION CHAMBER

DEPOSITION OF N-METAL FILMS

INTEGRATED PROCESS AND PROCESSING SYSTEM FOR MANUFACTURING PMOS TRANSISTORS

LINEAR ACCELERATOR HAVING ROBUST POWER FEEDTHROUGH

PROCESSING CHAMBER WITH GAS RECYCLING

SELECTIVE MATERIAL REMOVAL WITH ANGULAR BEAM

METHOD TO ENLARGE FEATURES IN SEMICONDUCTOR DEVICE LAYERS USING ION IMPLANTS OF DIFFERENT TEMPERATURES

Ion Beam-Induced Epitaxial Crystallization on an Integrated Processing Architecture

MEMRISTIVE COMPUTING SCHEMES IN THE BACK-END-OF-THE-LINE

MEMRISTIVE COMPUTING SCHEMES IN THE BACK-END-OF-THE-LINE

WIDE-BANDGAP SUPER JUNCTION STRUCTURES FOR POWER DEVICES

EPI LINER SUPER JUNCTION DEVICES WITH DIFFUSION BARRIER

TRENCH-BASED SUPER JUNCTION STRUCTURES VIA SIDEWALL DOPING

4F2 DRAM WITH BACKSIDE CONTACT

PARTICLE ACCELERATOR HAVING CONFIGURABLE QUADRUPOLE ASSEMBLY

NOVEL SWITCHING INDUCTOR

RAPID PROGRAMMING OF MEMORY ARRAYS WITH CONCURRENT PROGRAMMING AND VERIFICATION

USE BACK SIDE POWER VIAS FOR SIGNALS

DEEP TRENCH ISOLATION ETCHING

SELECTIVE ETCHING OF SILICON-CONTAINING MATERIAL

SELECTIVE ETCHING OF SILICON-AND-GERMANIUM-CONTAINING MATERIAL

TRANSISTOR BILAYER DIELECTRIC WALL

TRANSITION METAL CONTAINING CONTACT WITH REDUCED CONTACT RESISTIVITY

SEMICONDUCTOR DEVICES HAVING REDUCED CONTACT RESISTIVITY

HYBRID SEMICONDUCTOR GAS FLOW COMPONENTS WITH SMOOTH INTERNAL WALLS

MULTI-STATION SUBSTRATE PROCESSING CHAMBER WITH PRECISE TEMPERATURE AND FLOW CONTROL

Methods Of Operating A Spatial Deposition Tool

UNIFORM SILICON OXIDE ETCHING METHODS

DIRECTIONAL SELECTIVE FILL FOR SILICON GAP FILL PROCESSES

METHODS OF FORMING TRANSITION METAL DICHALCOGENIDE FILMS

MULTI-THRESHOLD VOLTAGE INTEGRATION SCHEMES FOR SEMICONDUCTOR DEVICES

Integrated CMOS Source Drain Formation With Advanced Control

TRANSISTOR DIRECT BACKSIDE CONTACT WITH ETCH STOP LAYER

DRAM CELL FABRICATION APPROACHES FOR DOPED MOLD

SACRIFICIAL METAL SIGNAL OR POWER LINE

INTERLOCK SYSTEM FOR PROCESSING CHAMBER EXHAUST ASSEMBLY

DEPOSITION RING FOR PHYSICAL VAPOR DEPOSITION CHAMBER