Austin, Texas
United States
62
2016-04-21
The entities that hold a legal rights for patent applications filed by inventor Hall Mark D.:
Mark D. Hall from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Semiconductor device with upset event detection and method of making
#2 | 2016-01-21Applications for nanopillar structures
#3 | 2015-10-01Method for forming a split-gate device
#4 | 2015-10-01Method for forming a split-gate device
#5 | 2015-09-03Method of making a logic transistor and non-volatile memory (NVM) cell
#6 | 2015-08-18Method for forming a split-gate device
#7 | 2015-02-05Methods of making semiconductor devices with non-volatile memory cells
#8 | 2015-01-15Systems and methods for reducing power consumption in semiconductor devices
#9 | 2014-10-09SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER
#10 | 2014-06-03Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique
#11 | 2014-05-15Semiconductor devices with non-volatile memory cells
#12 | 2014-05-06Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage
#13 | 2014-05-01Method of making a logic transistor and a non-volatile memory (NVM) cell
#14 | 2014-01-02Applications for nanopillar structures
#15 | 2013-12-12Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric
#16 | 2013-11-05Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric
#17 | 2013-10-10Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic
#18 | 2013-10-10Non-volatile memory (NVM) and logic integration
#19 | 2013-10-10Logic transistor and non-volatile memory cell integration
#20 | 2013-10-10Logic transistor and non-volatile memory cell integration
#21 | 2013-09-26Semiconductor devices with different dielectric thicknesses
#22 | 2013-08-22Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic
#23 | 2013-08-22Non-volatile memory cell and logic transistor integration
#24 | 2013-07-11Methods of making logic transistors and non-volatile memory cells
#25 | 2013-07-11Non-volatile memory (NVM) and logic integration
#26 | 2013-07-04Non-volatile memory (NVM) and logic integration
#27 | 2013-07-04Non-volatile memory (NVM) and logic integration
#28 | 2013-05-30Logic and non-volatile memory (NVM) integration
#29 | 2013-03-14Capacitive sensor radiation measurement
#30 | 2013-03-14Incident capacitive sensor
#31 | 2012-11-01Method of making a semiconductor device as a capacitor
#32 | 2012-11-01Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner
#33 | 2012-11-01Semiconductor device structure as a capacitor
#34 | 2012-10-25Decoupling capacitors recessed in shallow trench isolation
#35 | 2012-10-25Isolated capacitors within shallow trench isolation
#36 | 2012-10-04Non-volatile memory and logic circuit process integration
#37 | 2012-10-04Non-volatile memory and logic circuit process integration
#38 | 2012-07-12Methods of making multi-state non-volatile memory cells
#39 | 2012-05-03Non-volatile memory and logic circuit process integration
#40 | 2012-03-22Lateral capacitor and method of making
#41 | 2012-01-12SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS
#42 | 2011-12-01Method of forming a shared contact in a semiconductor device
#43 | 2011-12-01Angled ion implantation in a semiconductor device
#44 | 2010-02-04Semiconductor devices with extended active regions
#45 | 2009-04-30Semiconductor devices with different dielectric thicknesses
#46 | 2008-10-23Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner
#47 | 2008-09-11Trench formation in a semiconductor material
#48 | 2007-10-25Process of forming an electronic device including a layer formed using an inductively coupled plasma
#49 | 2007-10-25STI stressor integration for minimal phosphoric exposure and divot-free topography
#50 | 2007-09-27Method for forming a stressor structure
#51 | 2007-09-20Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility
#52 | 2007-09-06Treatment for reduction of line edge roughness
#53 | 2007-08-23Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration
#54 | 2007-08-23Poly pre-doping anneals for improved gate profiles
#55 | 2007-07-26EPI T-gate structure for CoSiextendibility
#56 | 2007-07-26Spacer T-gate structure for CoSiextendibility
#57 | 2007-06-21Semiconductor device having an organic anti-reflective coating (ARC) and method therefor
#58 | 2007-03-01Dual silicide semiconductor fabrication process
#59 | 2006-05-18Plasma treatment for surface of semiconductor device
#60 | 2005-08-18Semiconductor device having an organic anti-reflective coating (ARC) and method therefor
#61 | 2005-06-16Method for elimination of excessive field oxide recess for thin Si SOI
#62 | 2005-02-03Semiconductor device having an organic anti-reflective coating (ARC) and method therefor
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