Austin, Texas
United States
28
2024-03-07
The entities that hold a legal rights for patent applications filed by inventor Shippy David:
David Shippy from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
ACCELERATOR ARCHITECTURE ON A PROGRAMMABLE PLATFORM
#2 | 2019-02-28Accelerator architecture on a programmable platform
#3 | 2015-12-03Accelerator architecture on a programmable platform
#4 | 2009-02-12Time-of-life counter for handling instruction flushes from a queue
#5 | 2009-02-12Handling data cache misses out-of-order for asynchronous pipelines
#6 | 2008-09-18Dynamic power management in a processor design
#7 | 2008-07-10Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor
#8 | 2008-06-19High Frequency Stall Design
#9 | 2008-06-12Load address dependency mechanism system and method in a high frequency, low power processor system
#10 | 2007-08-23Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates
#11 | 2007-08-23Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system
#12 | 2007-08-02Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines
#13 | 2007-05-24System and method for dynamically selecting storage instruction performance scheme
#14 | 2007-04-19Method for dynamically choosing between varying processor error resolutions
#15 | 2007-04-19Method and apparatus for delaying a load miss flush until issuing the dependent instruction
#16 | 2007-04-12Time-of-life counter design for handling instruction flushes from a queue
#17 | 2007-04-12Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor
#18 | 2007-03-29Dynamic power management in a processor design
#19 | 2007-03-29Method and apparatus for issuing instructions from an issue queue in an information handling system
#20 | 2007-02-22System and method for high frequency stall design
#21 | 2006-12-21Fine grained multi-thread dispatch block mechanism
#22 | 2006-10-05System and method for handling multi-cycle non-pipelined instruction sequencing
#23 | 2006-09-05Memory management for real-time applications
#24 | 2006-05-18Load address dependency mechanism system and method in a high frequency, low power processor system
#25 | 2005-12-27Memory management in multiprocessor system
#26 | 2005-10-13Architected register file system utilizes status and control registers to control read/write operations between threads
#27 | 2005-03-10Software-controlled cache set management
#28 | 2005-03-10Software-controlled cache set management with software-generated class identifiers
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