Santa Clara, California
United States
23
2025-09-25
The entities that hold a legal rights for patent applications filed by inventor Debbage Mark:
Mark Debbage from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:
RELIABLE TRANSPORT ARCHITECTURE
#2 | 2023-12-21PACKET HEADER OPTIMIZATION IN ETHERNET INTERNET PROTOCOL NETWORKS
#3 | 2022-11-03Direct memory writes by network interface of a graphics processing unit
#4 | 2022-05-05COMMUNICATIONS FOR WORKLOADS
#5 | 2022-04-21SYSTEM FOR STORAGE OF RECEIVED MESSAGES
#6 | 2022-04-21SWITCH-ORIGINATED CONGESTION MESSAGES
#7 | 2022-04-14PACKET FORMAT ADJUSTMENT TECHNOLOGIES
#8 | 2022-03-17Scalable protocol-agnostic reliable transport
#9 | 2021-09-09System, apparatus, and method for streaming input/output data
#10 | 2021-04-22Reliable transport architecture
#11 | 2019-02-28Technologies for managing a latency-efficient pipeline through a network interface controller
#12 | 2018-02-08Optimized credit return mechanism for packet sends
#13 | 2017-08-31Sending packets using optimized PIO write sequences without sfences and out of order credit returns
#14 | 2017-08-17Optimized credit return mechanism for packet sends
#15 | 2017-06-29Reliable out-of order end-to-end protocol with robust window state overflow management and a multi-node system using same
#16 | 2017-06-22Sending packets using optimized PIO write sequences without SFENCES
#17 | 2017-01-19Sending packets using optimized PIO write sequences without sfences
#18 | 2016-12-22Sending packets using optimized PIO write sequences without sfences
#19 | 2016-11-03System, method and apparatus for improving the performance of collective operations in high performance computing
#20 | 2016-03-24System, method and apparatus for improving the performance of collective operations in high performance computing
#21 | 2015-12-31Optimized credit return mechanism for packet sends
#22 | 2015-12-31Sending packets using optimized PIO write sequences without SFENCEs
#23 | 2009-06-02Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
1402338 ⎘