Inventor profile of:

Yaakov Yaari

City:

Haifa

Country:

Israel

Published Applications:

33

Last publication date:

2016-08-25

Top Assignees for applications by Yaakov Yaari

The entities that hold a legal rights for patent applications filed by inventor Yaari Yaakov:

Recent patent applications by Yaari Yaakov

Yaakov Yaari from Haifa, IL has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2016-08-25
US20160246697A1
Physics

Hardware-based edge profiling

#2 | 2015-10-29
US20150310332A1
Physics

Predicting outcome based on input

#3 | 2014-01-23
US20140025997A1
Physics

Test selection

#4 | 2013-12-03
US10185896
-

Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register

#5 | 2013-05-16
US20130124835A1
Physics

Packing lower half bits of signed data elements in two source registers in a destination register with saturation

#6 | 2013-05-16
US20130124834A1
Physics

Packing odd bytes from two source registers of packed data

#7 | 2013-05-16
US20130124833A1
Physics

Orderly storing of corresponding packed bytes from first and second source registers in result register

#8 | 2013-05-16
US20130124832A1
Physics

Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements

#9 | 2013-05-16
US20130124831A1
Physics

Packing in destination register half of each element with saturation from two source packed data registers

#10 | 2013-05-16
US20130124830A1
Physics

Method and Apparatus for Unpacking Packed Data

#11 | 2013-05-09
US20130117547A1
Physics

Method and apparatus for unpacking and moving packed data

#12 | 2013-05-09
US20130117540A1
Physics

Processor executing unpack and pack instructions specifying two source packed data operands and saturation

#13 | 2013-05-09
US20130117539A1
Physics

Packing signed word elements from two source registers to saturated signed byte elements in destination register

#14 | 2013-05-09
US20130117538A1
Physics

Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers

#15 | 2013-05-09
US20130117537A1
Physics

Interleaving half of packed data elements of size specified in instruction and stored in two source registers

#16 | 2013-03-14
US20130067192A1
Physics

Data object profiling during program execution

#17 | 2012-08-02
US20120198210A1
Physics

Processor executing pack and unpack instructions

#18 | 2012-03-29
US20120078925A1
Physics

SEARCHING WITHIN LOG FILES

#19 | 2011-11-17
US20110283152A1
Physics

Detecting and optimizing false sharing

#20 | 2011-10-13
US20110252408A1
Physics

Performance optimization based on data accesses during critical sections

#21 | 2011-09-08
US20110219214A1
Physics

Packing two packed signed data in registers with saturation

#22 | 2011-04-21
US20110093682A1
Physics

Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation

#23 | 2009-07-30
US20090193402A1
Physics

Iterative Compilation Supporting Entity Instance-Specific Compiler Option Variations

#24 | 2009-05-21
US20090133005A1
Physics

METHOD FOR VALIDATION OF BINARY CODE TRANSFORMATIONS

#25 | 2009-05-05
US12060238
-

Method and system for detecting runtime defects in a program by comparing correct and incorrect runs

#26 | 2009-01-20
US10846726
-

Method and apparatus for executing packed shift operations

#27 | 2008-09-30
US11940750
-

Method for validation of binary code transformations

#28 | 2007-10-11
US20070239810A1
Physics

Method and apparatus for providing packed shift operations in a processor

#29 | 2007-07-05
US20070157178A1
Physics

Cross-module program restructuring

#30 | 2006-10-19
US20060236076A1
Physics

Interleaving saturated lower half of data elements from two source registers of packed data

#31 | 2006-10-19
US20060235914A1
Physics

Method and apparatus for providing packed shift operations in a processor

#32 | 2005-10-06
US20050219897A1
Physics

Method and apparatus for providing packed shift operations in a processor

#33 | 2005-05-31
US10623062
-

Method and apparatus for performing packed shift operations

InventorID:

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