Terry Parks

APPARATUS AND METHOD FOR MANAGING DEPRECATED INSTRUCTION SET ARCHITECTURE (ISA) FEATURES

FAST SEGMENTATION

MEMORY CONTROLLER ZERO CACHE

Zero bits in L3 tags

Dynamic reconfiguration of multi-core processor

Neural network unit that interrupts processing core upon condition

Neural network unit that interrupts processing core upon condition

Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode

Microprocessor that fuses if-then instructions

Processor with memory controller including dynamically programmable functional unit

Sanitize-aware DRAM controller

Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests

Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests

Processor with an expandable instruction set architecture for dynamically configuring execution resources

Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

Neural network unit employing user-supplied reciprocal for normalizing an accumulated value

Neural network unit with shared activation function units

Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value

Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network LSTM cells

Neural network unit that performs convolutions using collective shift register among array of neural processing units

Multi-operation neural network unit

Processor with hybrid coprocessor/execution unit neural network unit

Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory

Neural network unit that performs concurrent LSTM cell calculations

Neural network unit with plurality of selectable output functions

Neural network unit with output buffer feedback for performing recurrent neural network computations

Neural network unit with neural processing units dynamically configurable to process multiple data sizes

Processor with architectural neural network execution unit

Tri-configuration neural network unit

Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource

Processor with variable rate execution unit

Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor

Neural network unit with output buffer feedback and masking capability

Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory

Apparatus employing user-specified binary point fixed point arithmetic

Neural network unit that performs stochastic rounding

Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state

Hardware data compressor using dynamic hash algorithm based on input block type

Cache replacement policy that considers memory access type

Hardware data compressor that sorts hash chains based on node string match probabilities

Hardware data compressor using dynamic hash algorithm based on input block type

Hardware data compressor with multiple string match search hash tables each based on different hash size

Hardware data compressor that directly huffman encodes output tokens from LZ77 engine

Processor including load EPT instruction

Microprocessor using compressed and uncompressed microcode storage

Microprocessor with arm and X86 instruction length decoders

ASYMMETRIC PROCESSOR WITH CORES THAT SUPPORT DIFFERENT ISA INSTRUCTION SUBSETS

Centralized synchronization mechanism for a multi-core processor

Key expansion logic using decryption key primitives

Microprocessor with on-the-fly switching of decryption keys

Microprocessor with secure execution mode and store key instructions

Decryption of encrypted instructions using keys selected on basis of instruction fetch address

Compressing instruction queue for a microprocessor

Efficient address translation caching in a processor that supports a large number of different address spaces

Processor that recovers from excessive approximate computing error

Processor with approximate computing execution unit that includes an approximation control register having an approximation mode flag, an approximation amount, and an error threshold, where the approximation control register is writable by an instruction set instruction

Processor that performs approximate computing instructions

Fractional use of prediction history storage for operating system routines

Selectively compressed microcode

Microprocessor with compressed and uncompressed microcode memories

Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match

Microprocessor with integrated NOP slide detector

Multi-core synchronization mechanism

Core synchronization mechanism in a multi-die multi-core microprocessor

Dynamic reconfiguration of multi-core processor

Inter-core communication via uncore RAM

Microprocessor with boot indicator that indicates a boot ISA of the microprocessor as either the X86 ISA or the ARM ISA

Multi-core hardware semaphore in non-architectural address space

Multi-core processor having control unit that generates interrupt requests to all cores in response to synchronization condition

Single core wakeup multi-core synchronization mechanism

Selective accumulation and use of predicting unit history

Microprocessor that fuses if-then instructions

Asymmetric multi-core processor with native switching mechanism

Uncore microcode ROM

Microprocessor that facilitates task switching between encrypted and unencrypted programs

Microprocessor that securely decrypts and executes encrypted instructions

Method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program

Apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor

Microprocessor that translates conditional load/store instructions into variable number of microinstructions

Conditional store instructions in an out-of-order execution microprocessor

Revokeable MSR password protection

Conditional load instructions in an out-of-order execution microprocessor

Running state power saving via reduced instructions per clock operation

Conditional non-branch instruction prediction

Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)

Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor

Efficient conditional ALU instruction in read-port limited register file microprocessor

EMULATION OF EXECUTION MODE BANKED REGISTERS

Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor

Generating constant for microinstructions from modified immediate field during instruction translation

Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline

Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA

Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline

Heterogeneous ISA microprocessor with shared hardware ISA registers

Load multiple and store multiple instructions in a microprocessor that emulates banked registers

Microprocessor that fetches and decrypts encrypted instructions in same time as plain text instructions

Revokeable MSR password protection

Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions

Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key values