FREMONT, California
United States
95
2010-11-30
92
2010-11-30
These are the the leading inventors for applications assigned to IP-FIRST, LLC:
IP-FIRST, LLC based in FREMONT, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Microprocessor apparatus and method for performing block cipher cryptographic functions
#2 | 2009-06-09 ✅ Patent 7,546,446 granted on 2009-06-09Selective interrupt suppression
#3 | 2009-06-02 ✅ Patent 7,542,566 granted on 2009-06-02Apparatus and method for performing transparent cipher block chaining mode cryptographic functions
#4 | 2009-05-12 ✅ Patent 7,532,722 granted on 2009-05-12Apparatus and method for performing transparent block cipher cryptographic functions
#5 | 2008-07-01 ✅ Patent 7,395,412 granted on 2008-07-01Apparatus and method for extending data modes in a microprocessor
#6 | 2008-05-27 ✅ Patent 7,380,109 granted on 2008-05-27Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor
#7 | 2008-05-27 ✅ Patent 7,380,103 granted on 2008-05-27Apparatus and method for selective control of results write back
#8 | 2008-05-13 ✅ Patent 7,373,483 granted on 2008-05-13Mechanism for extending the number of registers in a microprocessor
#9 | 2008-02-05 ✅ Patent 7,328,328 granted on 2008-02-05Non-temporal memory reference control mechanism
#10 | 2008-01-22 ✅ Patent 7,321,910 granted on 2008-01-22Microprocessor apparatus and method for performing block cipher cryptographic functions
#11 | 2008-01-17EARLY ACCESS TO MICROCODE ROM
#12 | 2008-01-01 ✅ Patent 7,315,921 granted on 2008-01-01Apparatus and method for selective memory attribute control
#13 | 2007-11-27 ✅ Patent 7,302,551 granted on 2007-11-27Suppression of store checking
#14 | 2007-10-30 ✅ Patent 7,288,980 granted on 2007-10-30Multiple mode clock receiver
#15 | 2007-10-04 ✅ Patent 7,647,478 granted on 2010-01-12Suppression of store checking
#16 | 2007-10-04 ✅ Patent 7,647,479 granted on 2010-01-12Non-temporal memory reference control mechanism
#17 | 2007-08-28 ✅ Patent 7,263,585 granted on 2007-08-28Store-induced instruction coherency mechanism
#18 | 2007-05-24 ✅ Patent 7,849,120 granted on 2010-12-07Microprocessor with random number generator and instruction for storing random data
#19 | 2007-05-24 ✅ Patent 7,818,358 granted on 2010-10-19Microprocessor with random number generator and instruction for storing random data
#20 | 2007-05-17 ✅ Patent 7,712,105 granted on 2010-05-04Microprocessor including random number generator supporting operating system-independent multitasking operation
#21 | 2007-05-15 ✅ Patent 7,219,112 granted on 2007-05-15Microprocessor with instruction translator for translating an instruction for storing random data bytes
#22 | 2007-04-12 ✅ Patent 7,631,172 granted on 2009-12-08Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
#23 | 2007-04-12 ✅ Patent 7,562,192 granted on 2009-07-14Microprocessor, apparatus and method for selective prefetch retire
#24 | 2007-04-05 ✅ Patent 8,296,345 granted on 2012-10-23Microprocessor with selectively available random number generator based on self-test result
#25 | 2007-04-03 ✅ Patent 7,200,740 granted on 2007-04-03Apparatus and method for speculatively performing a return instruction in a microprocessor
#26 | 2007-03-22 ✅ Patent 7,383,394 granted on 2008-06-03Microprocessor, apparatus and method for selective prefetch retire
#27 | 2007-03-20 ✅ Patent 7,193,445 granted on 2007-03-20Non-inverting domino register
#28 | 2007-03-13 ✅ Patent 7,191,291 granted on 2007-03-13Microprocessor with variable latency stack cache
#29 | 2007-03-06 ✅ Patent 7,188,215 granted on 2007-03-06Apparatus and method for renaming a cache line
#30 | 2007-02-27 ✅ Patent 7,185,186 granted on 2007-02-27Apparatus and method for resolving deadlock fetch conditions involving branch target address cache
#31 | 2007-02-27 ✅ Patent 7,185,180 granted on 2007-02-27Apparatus and method for selective control of condition code write back
#32 | 2007-02-20 ✅ Patent 7,181,596 granted on 2007-02-20Apparatus and method for extending a microprocessor instruction set
#33 | 2007-02-13 ✅ Patent 7,178,010 granted on 2007-02-13Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack
#34 | 2007-02-06 ✅ Patent 7,174,355 granted on 2007-02-06Random number generator with selectable dual random bit string engines
#35 | 2007-01-16 ✅ Patent 7,165,168 granted on 2007-01-16Microprocessor with branch target address cache update queue
#36 | 2007-01-16 ✅ Patent 7,165,084 granted on 2007-01-16Microprocessor with selectivity available random number generator based on self-test result
#37 | 2007-01-16 ✅ Patent 7,165,169 granted on 2007-01-16Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
#38 | 2007-01-09 ✅ Patent 7,162,612 granted on 2007-01-09Mechanism in a microprocessor for executing native instructions directly from memory
#39 | 2007-01-02 ✅ Patent 7,159,097 granted on 2007-01-02Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts
#40 | 2006-12-26 ✅ Patent 7,155,598 granted on 2006-12-26Apparatus and method for conditional instruction execution
#41 | 2006-12-19 ✅ Patent 7,152,154 granted on 2006-12-19Apparatus and method for invalidation of redundant branch target address cache entries
#42 | 2006-12-12 ✅ Patent 7,149,764 granted on 2006-12-12Random number generator bit string filter
#43 | 2006-11-28 ✅ Patent 7,143,269 granted on 2006-11-28Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor
#44 | 2006-11-21 ✅ Patent 7,139,877 granted on 2006-11-21Microprocessor and apparatus for performing speculative load operation from a stack memory cache
#45 | 2006-11-21 ✅ Patent 7,139,876 granted on 2006-11-21Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache
#46 | 2006-11-21 ✅ Patent 7,139,785 granted on 2006-11-21Apparatus and method for reducing sequential bit correlation in a random number generator
#47 | 2006-11-14 ✅ Patent 7,136,990 granted on 2006-11-14Fast POP operation from RAM cache using cache row value stack
#48 | 2006-11-09 ✅ Patent 7,334,009 granted on 2008-02-19Microprocessor with random number generator and instruction for storing random data
#49 | 2006-11-07 ✅ Patent 7,133,968 granted on 2006-11-07Method and apparatus for resolving additional load misses in a single pipeline processor under stalls of instructions not accessing memory-mapped I/O regions
#50 | 2006-11-07 ✅ Patent 7,134,005 granted on 2006-11-07Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte
#51 | 2006-10-31 ✅ Patent 7,131,083 granted on 2006-10-31Optimization of clock network capacitance on an integrated circuit
#52 | 2006-10-17 ✅ Patent 7,124,314 granted on 2006-10-17Method and apparatus for fine tuning clock signals of an integrated circuit
#53 | 2006-09-19 ✅ Patent 7,111,125 granted on 2006-09-19Apparatus and method for renaming a data block within a cache
#54 | 2006-08-08 ✅ Patent 7,089,371 granted on 2006-08-08Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of cache lines from memory
#55 | 2006-08-08 ✅ Patent 7,089,368 granted on 2006-08-08Microprocessor apparatus and method for exclusively prefetching a block of cache lines from memory
#56 | 2006-07-18 ✅ Patent 7,080,211 granted on 2006-07-18Microprocessor apparatus and method for prefetch, allocation, and initialization of a cache line from memory
#57 | 2006-07-18 ✅ Patent 7,080,210 granted on 2006-07-18Microprocessor apparatus and method for exclusive prefetch of a cache line from memory
#58 | 2006-03-23 ✅ Patent 7,146,468 granted on 2006-12-05Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache
#59 | 2006-03-23Continuous multi-buffering random number generator
#60 | 2006-02-14 ✅ Patent 6,998,875 granted on 2006-02-14Output driver impedance controller
#61 | 2006-02-14 ✅ Patent 7,000,081 granted on 2006-02-14Write back and invalidate mechanism for multiple cache lines
#62 | 2006-01-31 ✅ Patent 6,993,738 granted on 2006-01-31Method for allocating spare cells in auto-place-route blocks
#63 | 2006-01-24 ✅ Patent 6,990,558 granted on 2006-01-24Microprocessor, apparatus and method for selective prefetch retire
#64 | 2006-01-17 ✅ Patent 6,988,172 granted on 2006-01-17Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status
#65 | 2006-01-12 ✅ Patent 7,234,045 granted on 2007-06-19Apparatus and method for handling BTAC branches that wrap across instruction cache lines
#66 | 2006-01-10 ✅ Patent 6,985,008 granted on 2006-01-10Apparatus and method for precisely controlling termination impedance
#67 | 2006-01-10 ✅ Patent 6,985,999 granted on 2006-01-10Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests
#68 | 2005-12-15 ✅ Patent 7,240,163 granted on 2007-07-03Microprocessor, apparatus and method for selective prefetch retire
#69 | 2005-12-08 ✅ Patent 6,983,358 granted on 2006-01-03Method and apparatus for maintaining status coherency between queue-separated functional units
#70 | 2005-11-24 ✅ Patent 7,076,639 granted on 2006-07-11Apparatus and method for masked move to and from flags register in a processor
#71 | 2005-11-15 ✅ Patent 6,965,254 granted on 2005-11-15Dynamic logic register
#72 | 2005-11-08 ✅ Patent 6,963,228 granted on 2005-11-08Complementary input dynamic logic
#73 | 2005-10-18 ✅ Patent 6,956,405 granted on 2005-10-18Teacher-pupil flip-flop
#74 | 2005-09-27 ✅ Patent 6,949,949 granted on 2005-09-27Apparatus and method for adjusting the impedance of an output driver
#75 | 2005-09-22 ✅ Patent 7,117,347 granted on 2006-10-03Processor including fallback branch prediction mechanism for far jump and far call instructions
#76 | 2005-09-08 ✅ Patent 7,162,619 granted on 2007-01-09Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
#77 | 2005-09-08 ✅ Patent 7,203,824 granted on 2007-04-10Apparatus and method for handling BTAC branches that wrap across instruction cache lines
#78 | 2005-08-11 ✅ Patent 6,931,517 granted on 2005-08-16Pop-compare micro instruction for repeat string operations
#79 | 2005-08-09 ✅ Patent 6,928,537 granted on 2005-08-09Split history tables for branch prediction
#80 | 2005-08-02 ✅ Patent 6,924,670 granted on 2005-08-02Complementary input dynamic muxed-decoder
#81 | 2005-06-30 ✅ Patent 7,039,793 granted on 2006-05-02Microprocessor apparatus and method for accelerating execution of repeat string instructions
#82 | 2005-06-16Speculative hybrid branch direction predictor
#83 | 2005-06-07 ✅ Patent 6,903,582 granted on 2005-06-07Integrated circuit timing debug apparatus and method
#84 | 2005-05-26 ✅ Patent 7,398,377 granted on 2008-07-08Apparatus and method for target address replacement in speculative branch target address cache
#85 | 2005-05-17 ✅ Patent 6,895,498 granted on 2005-05-17Apparatus and method for target address replacement in speculative branch target address cache
#86 | 2005-05-12 ✅ Patent 7,543,134 granted on 2009-06-02Apparatus and method for extending a microprocessor instruction set
#87 | 2005-04-26 ✅ Patent 6,886,023 granted on 2005-04-26Apparatus for generating random numbers
#88 | 2005-04-26 ✅ Patent 6,886,093 granted on 2005-04-26Speculative hybrid branch direction predictor
#89 | 2005-04-14 ✅ Patent 7,234,025 granted on 2007-06-19Microprocessor with repeat prefetch instruction
#90 | 2005-04-07 ✅ Patent 7,237,098 granted on 2007-06-26Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
#91 | 2005-03-22 ✅ Patent 6,871,206 granted on 2005-03-22Continuous multi-buffering random number generator
#92 | 2005-03-10 ✅ Patent 7,173,456 granted on 2007-02-06Dynamic logic return-to-zero latching mechanism
#93 | 2005-03-01 ✅ Patent 6,862,704 granted on 2005-03-01Apparatus and method for testing memory in a microprocessor
#94 | 2005-03-01 ✅ Patent 6,862,670 granted on 2005-03-01Tagged address stack and microprocessor using same
#95 | 2005-02-24 ✅ Patent 7,159,098 granted on 2007-01-02Selecting next instruction line buffer stage based on current instruction line boundary wraparound and branch target in buffer indicator
259389 ⎘