Haifa
Israel
64
2019-11-28
The entities that hold a legal rights for patent applications filed by inventor Eitan Benny:
Benny Eitan from Haifa, IL has applied for patents for these inventions. The list has both pending applications and granted patents:
Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions
#2 | 2018-08-09Floating point scaling processors, methods, systems, and instructions
#3 | 2018-08-09Floating point scaling processors, methods, systems, and instructions
#4 | 2018-07-19Floating point scaling processors, methods, systems, and instructions
#5 | 2018-05-03In-lane vector shuffle instructions
#6 | 2018-04-26In-lane vector shuffle instructions
#7 | 2018-04-26In-lane vector shuffle instructions
#8 | 2018-04-26In-lane vector shuffle instructions
#9 | 2017-09-21In-lane vector shuffle instructions
#10 | 2017-07-13Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions
#11 | 2017-03-09Floating point scaling processors, methods, systems, and instructions
#12 | 2015-03-26Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructions
#13 | 2015-03-26Floating point scaling processors, methods, systems, and instructions
#14 | 2014-08-07Math circuit for estimating a transcendental function
#15 | 2014-05-01Techniques for connected component labeling
#16 | 2013-12-03Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register
#17 | 2013-10-31Floating point rounding processors, methods, systems, and instructions
#18 | 2013-10-03PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA
#19 | 2013-10-03PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA
#20 | 2013-08-22Processor for performing multiply-add operations on packed data
#21 | 2013-08-15Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits
#22 | 2013-08-01Processor for performing multiply-add operations on packed data
#23 | 2013-07-25Instructions and logic to perform mask load and store operations as sequential or one-at-a-time operations after exceptions and for un-cacheable type memory
#24 | 2013-05-16Packing lower half bits of signed data elements in two source registers in a destination register with saturation
#25 | 2013-05-16Packing odd bytes from two source registers of packed data
#26 | 2013-05-16Orderly storing of corresponding packed bytes from first and second source registers in result register
#27 | 2013-05-16Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements
#28 | 2013-05-16Packing in destination register half of each element with saturation from two source packed data registers
#29 | 2013-05-09Method and apparatus for unpacking and moving packed data
#30 | 2013-05-09Processor executing unpack and pack instructions specifying two source packed data operands and saturation
#31 | 2013-05-09Packing signed word elements from two source registers to saturated signed byte elements in destination register
#32 | 2013-05-09Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers
#33 | 2013-05-09Interleaving half of packed data elements of size specified in instruction and stored in two source registers
#34 | 2013-04-11Processor for performing multiply-add operations on packed data
#35 | 2013-03-14Instructions with floating point control override
#36 | 2012-12-27Processor for performing multiply-add operations on packed data
#37 | 2012-08-23Processor for performing multiply-add operations on packed data
#38 | 2012-08-02Processor executing pack and unpack instructions
#39 | 2012-06-28Performing reciprocal instructions with high accuracy
#40 | 2012-03-29Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions
#41 | 2011-12-15Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits
#42 | 2011-10-27Method and apparatus for performing multiply-add operations on packed data
#43 | 2011-09-08Packing two packed signed data in registers with saturation
#44 | 2011-06-23Multiplying and adding matrices
#45 | 2011-04-21Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation
#46 | 2009-10-22Processor for performing multiply-add operations on packed data
#47 | 2009-07-02Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation
#48 | 2009-07-02Mixing instructions with different register sizes
#49 | 2009-07-02Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
#50 | 2009-07-02Instructions with floating point control override
#51 | 2009-06-25Method and apparatus for a double width load using a single width load port
#52 | 2009-03-24Method and apparatus for performing multiply-add operations on packed data
#53 | 2009-01-20Method and apparatus for executing packed shift operations
#54 | 2008-09-09Method and apparatus for performing multiply-add operations on packed data
#55 | 2008-07-01Method and apparatus for performing multiply-add operations on packed data
#56 | 2008-05-13Emptying packed data state during execution of packed data instructions
#57 | 2007-10-11Method and apparatus for providing packed shift operations in a processor
#58 | 2006-12-12Processor with instructions that operate on different data types stored in the same single logical register file
#59 | 2006-10-19Interleaving saturated lower half of data elements from two source registers of packed data
#60 | 2006-10-19Method and apparatus for providing packed shift operations in a processor
#61 | 2005-10-06Method and apparatus for providing packed shift operations in a processor
#62 | 2005-08-23Methods and apparatus for determination of packet sizes when transferring packets via a network
#63 | 2005-05-31Method and apparatus for performing packed shift operations
#64 | 2005-02-17Processor with instructions that operate on different data types stored in the same single logical register file
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