Plano, Texas
United States
28
2017-06-22
The entities that hold a legal rights for patent applications filed by inventor Jiang Ping:
Ping Jiang from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Low damage low-k dielectric etch
#2 | 2017-05-25Method of fabricating semiconductors
#3 | 2016-11-08Method of fabricating semiconductors
#4 | 2016-03-03Capacitor combination stress testing
#5 | 2011-06-16Poison-free and low ULK damage integration scheme for damascene interconnects
#6 | 2011-02-10SILICON CARBIDE FILM FOR INTEGRATED CIRCUIT FABRICATION
#7 | 2010-02-18FUSI integration method using SOG as a sacrificial planarization layer
#8 | 2009-07-14Etching systems and processing gas specie modulation
#9 | 2009-04-30FUSI integration method using SOG as a sacrificial planarization layer
#10 | 2009-03-26SiC Film for Semiconductor Processing
#11 | 2009-01-15Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics
#12 | 2008-12-11Poison-free and low ULK damage integration scheme for damascene interconnects
#13 | 2008-12-04DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATION FOR PROTECTING LOW-K DIELECTRICS
#14 | 2008-04-17Gas switching during an etch process to modulate the characteristics of the etch
#15 | 2008-03-06METHOD FOR PREVENTION OF RESIST POISONING IN INTEGRATED CIRCUIT FABRICATION
#16 | 2008-01-31Method and system for controlling the uniformity of a ballistic electron beam by RF modulation
#17 | 2007-11-29Gas switching during an etch process to modulate the characteristics of the etch
#18 | 2007-07-26FUSI integration method using SOG as a sacrificial planarization layer
#19 | 2007-05-08Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
#20 | 2007-03-22Semiconductor Device Having a Fully Silicided Gate Electrode and Method of Manufacture Therefor
#21 | 2007-02-22Methods to facilitate etch uniformity and selectivity
#22 | 2006-10-31Dual cap layer in damascene interconnection processes
#23 | 2005-11-24Integration scheme for using silicided dual work function metal gates
#24 | 2005-11-17Plasma treatment for silicon-based dielectrics
#25 | 2005-11-03In-situ etch-stop etch and ashing in association with damascene processing in forming semiconductor interconnect structures
#26 | 2005-09-29Semiconductor device having a fully silicided gate electrode and method of manufacture therefor
#27 | 2005-09-29Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
#28 | 2005-05-31BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control
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