Beaverton, Oregon
United States
41
2021-06-03
The entities that hold a legal rights for patent applications filed by inventor Sung Seung Hoon:
Seung Hoon Sung from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Deep gate-all-around semiconductor device having germanium or group III-V active layer
#2 | 2019-06-06III-N epitaxial device structures on free standing silicon mesas
#3 | 2018-10-18Deep gate-all-around semiconductor device having germanium or group III-V active layer
#4 | 2018-08-02III-N epitaxial device structures on free standing silicon mesas
#5 | 2017-11-09Group III-N transistor on nanoscale template structures
#6 | 2017-09-07Methods and structures to prevent sidewall defects during selective epitaxy
#7 | 2017-08-17LOW SHEET RESISTANCE GaN CHANNEL ON Si SUBSTRATE USING InAlN AND AlGaN BI-LAYER CAPPING STACK
#8 | 2017-07-20III-N devices in Si trenches
#9 | 2017-07-06Deep gate-all-around semiconductor device having germanium or group III-V active layer
#10 | 2017-06-08TRENCH CONFINED EPITAXIALLY GROWN DEVICE LAYER(S)
#11 | 2017-06-01Variable gate width for gate all-around transistors
#12 | 2017-05-11Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation
#13 | 2017-01-19III-N transistors with enhanced breakdown voltage
#14 | 2016-10-06Nonplanar III-N transistors with compositionally graded semiconductor channels
#15 | 2016-08-18Group III-N transistors on nanoscale template structures
#16 | 2016-08-11Deep gate-all-around semiconductor device having germanium or group III-V active layer
#17 | 2016-07-14Forming III-V device structures on (111) planes of silicon fins
#18 | 2016-07-14Composite High-K Metal Gate Stack for Enhancement Mode GaN Semiconductor Devices
#19 | 2016-06-23Methods and structures to prevent sidewall defects during selective epitaxy
#20 | 2016-03-03Group III-N transistors on nanoscale template structures
#21 | 2015-12-03Deep gate-all-around semiconductor device having germanium or group III-V active layer
#22 | 2015-11-05Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation
#23 | 2015-09-24Methods of containing defects for non-silicon device engineering
#24 | 2015-07-23III-N devices in Si trenches
#25 | 2015-07-02Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack
#26 | 2015-05-14Nanowire transistor fabrication with hardmask layers
#27 | 2015-05-07Gas reactor devices with microplasma arrays encapsulated in defect free oxide
#28 | 2015-04-23Group III-N transistor on nanoscale template structures
#29 | 2015-03-05Nonplanar III-N transistors with compositionally graded semiconductor channels
#30 | 2014-10-02Trench confined epitaxially grown device layer(s)
#31 | 2014-10-02Group III-N transistors on nanoscale template structures
#32 | 2014-08-21Methods of containing defects for non-silicon device engineering
#33 | 2014-07-24Deep gate-all-around semiconductor device having germanium or group III-V active layer
#34 | 2014-06-26Nonplanar III-N transistors with compositionally graded semiconductor channels
#35 | 2014-06-26Epitaxial film growth on patterned substrate
#36 | 2014-06-19Group III-N transistors on nanoscale template structures
#37 | 2014-04-03Methods of containing defects for non-silicon device engineering
#38 | 2014-04-03Trench confined epitaxially grown device layer(s)
#39 | 2014-04-03Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation
#40 | 2013-12-26Variable gate width for gate all-around transistors
#41 | 2013-03-21Arrays of metal and metal oxide microplasma devices with defect free oxide
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