GILBERT DEWEY

ASYMMETRIC STACKS OF NMOS AND PMOS TRANSISTORS IN A HYBRID CMOS ARCHITECTURE

GERMANIUM-RICH METAL CONTACT LAYERS FOR PMOS SOURCE AND DRAIN CONTACTS

CHALCOGEN-DOPED NMOS SOURCE AND DRAIN CONTACTS

TECHNOLOGIES FOR STRAIN ENGINEERING IN GATE-ALL-AROUND TRANSISTORS

TRANSISTOR WITH LINER-LAST SOURCE AND DRAIN TRENCH CONTACTS, AND METHODS OF MAKING SAME

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING MIXED CFET ARCHITECTURES

INTEGRATED CIRCUIT STRUCTURES WITH VARIED PERCENTAGE-GE SILICON GERMANIUM NANOWIRES

ARCHITECTURES AND METHODS FOR DIFFERENTIAL CMOS CONTACT PROFILES

JUMPER GATE FOR ADVANCED INTEGRATED CIRCUIT STRUCTURES

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PATTERNED NANOWIRE SCALING

STACKED TRANSISTOR ARCHITECTURES INCLUDING SOURCE & DRAIN STRUCTURES WITH MOLYBDENUM

CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES

INTEGRATED CIRCUIT STRUCTURE WITH ASYMMETRIC EPITAXIAL SOURCE OR DRAIN ARRANGEMENTS

SOURCE/DRAIN CONTACT TRENCH WITH DIELECTRIC LINER ON CONTACT METAL

TRANSISTORS WITH ASYMMETRIC SOURCE AND DRAIN CONTACTS

CAPPING NANORIBBON FINS IN SUPERLATTICE STRUCTURES DURING FABRICATION

CMOS METAL CONTACTS WITH DOPANT DIFFUSION BARRIERS

INCORPORATION OF SEMICONDUCTOR DOPING MATERIALS IN METAL CONTACTS VIA REACTIVE SPUTTERING

RIBBON OR WIRE TRANSISTOR STACK WITH SELECTIVE DIPOLE THRESHOLD VOLTAGE SHIFTER

INTEGRATED CIRCUIT STRUCTURE WITH DIFFERENTIATED SOURCE OR DRAIN STRUCTURES

ARRAYS OF DOUBLE-SIDED DRAM CELLS INCLUDING CAPACITORS ON THE FRONTSIDE AND BACKSIDE OF A STACKED TRANSISTOR STRUCTURE

SELF-ALIGNED MEMORY CELL WITH REPLACEMENT METAL GATE VERTICAL ACCESS TRANSISTOR AND STACKED 3D CAPACITORS

BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES

CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES

STACKED FORKSHEET TRANSISTORS

SPUTTER TARGETS FOR SELF-DOPED SOURCE AND DRAIN CONTACTS

Sideways vias in isolation areas to contact interior layers in stacked devices

Stacked source-drain-gate connection and process for forming such

Transistor with isolation below source and drain

TOP-GATE DOPED THIN FILM TRANSISTOR

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BOTTOM-UP OXIDATION APPROACH

LOW-RESISTANCE AND THERMALLY STABLE CONTACTS WITH BORIDE, INDIUM, OR GALLIUM METAL COMPOUND LAYERS

LOW-RESISTANCE AND THERMALLY STABLE CONTACTS WITH PHOSPHIDE OR ARSENIDE METAL COMPOUND LAYERS

SOURCE AND DRAIN REFRACTORY METAL CAP

CAPPING SOURCE AND DRAIN REGIONS OF TRANSISTORS TO PREVENT DIFFUSION OF DOPANTS DURING FABRICATION

LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES

SIGE:GAB SOURCE OR DRAIN STRUCTURES WITH LOW RESISTIVITY

SPUTTER TARGETS AND SOURCES FOR SELF-DOPED SOURCE AND DRAIN CONTACTS

Forming an oxide volume within a fin

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING MULTIPLE BOTTOM-UP OXIDATION APPROACHES

CONDUCTIVE CONTACTS WRAPPED AROUND EPITAXIAL SOURCE OR DRAIN REGIONS

Stacked source-drain-gate connection and process for forming such

LOW TEMPERATURE, HIGH GERMANIUM, HIGH BORON SIGE:B PEPI WITH TITANIUM SILICIDE CONTACTS FOR ULTRA-LOW PMOS CONTACT RESISTIVITY AND THERMAL STABILITY

WRAP-AROUND CONTACTS FOR STACKED TRANSISTORS

CONTACT OVER ACTIVE GATE STRUCTURES WITH TRENCH CONTACT LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

NON-REACTIVE EPI CONTACT FOR STACKED TRANSISTORS

SOURCE OR DRAIN METALLIZATION PRIOR TO CONTACT FORMATION IN STACKED TRANSISTORS

FRONTSIDE AND BACKSIDE EPI CONTACT

TITANIUM CONTACT FORMATION

STACKED TRANSISTORS WITH REMOVED EPI BARRIER

JUMPER GATE FOR ADVANCED INTEGRATED CIRCUIT STRUCTURES

Stacked trigate transistors with dielectric isolation and process for forming such

ENRICHED SEMICONDUCTOR NANORIBBONS FOR PRODUCING INTRINSIC COMPRESSIVE STRAIN

LAYER TRANSFER PROCESS TO FORM BACKSIDE CONTACTS IN SEMICONDUCTOR DEVICES

CLADDING AND CONDENSATION FOR STRAINED SEMICONDUCTOR NANORIBBONS

FORMATION OF GATE SPACERS FOR STRAINED PMOS GATE-ALL-AROUND TRANSISTOR STRUCTURES

STEPWISE INTERNAL SPACERS FOR STACKED TRANSISTOR STRUCTURES

SILICON RICH CAPPING LAYER PRE-AMORPHIZED WITH GERMANIUM AND BORON IMPLANTS FOR THERMAL STABILITY AND LOW PMOS CONTACT RESISTIVITY

CMOS ARCHITECTURE WITH THERMALLY STABLE SILICIDE GATE WORKFUNCTION METAL

LOW TEMPERATURE, HIGH GERMANIUM, HIGH BORON SIGE:B PEPI WITH A SILICON RICH CAPPING LAYER FOR ULTRA-LOW PMOS CONTACT RESISTIVITY AND THERMAL STABILITY

GATE-TO-GATE ISOLATION FOR STACKED TRANSISTOR ARCHITECTURE VIA SELECTIVE DIELECTRIC DEPOSITION STRUCTURE

Transistor including wrap around source and drain contacts

Ferroelectric gate stack for band-to-band tunneling reduction

LOW GERMANIUM, HIGH BORON SILICON RICH CAPPING LAYER FOR PMOS CONTACT RESISTANCE THERMAL STABILITY

CO-DEPOSITION OF TITANIUM AND SILICON FOR IMPROVED SILICON GERMANIUM SOURCE AND DRAIN CONTACTS

Backside contacts for semiconductor devices

Isolation wall stressor structures to improve channel stress and their methods of fabrication

Metallization structures for stacked device connectivity and their methods of fabrication

Top-gate doped thin film transistor

Thin-film transistors and MIM capacitors in exclusion zones

Non-silicon N-type and P-type stacked transistors for integrated circuit devices

Leave-behind protective layer having secondary purpose

Stacked thin film transistors with nanowires

Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure

Ribbon or wire transistor stack with selective dipole threshold voltage shifter

INTEGRATED CIRCUIT STRUCTURES HAVING GESNB SOURCE OR DRAIN STRUCTURES

Thin film transistors with spacer controlled gate length

Thin film transistors having U-shaped features

Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

Isolation walls for vertically stacked transistor structures

LOW RESISTANCE AND REDUCED REACTIVITY APPROACHES FOR FABRICATING CONTACTS AND THE RESULTING STRUCTURES

Low resistance approaches for fabricating contacts and the resulting structures

Dual contact process with stacked metal layers

DUAL CONTACT PROCESS WITH SELECTIVE DEPOSITION

Transistor with isolation below source and drain

CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES

Stacked forksheet transistors

Halogen treatment for NMOS contact resistance improvement

Antiferroelectric gate dielectric transistors and their methods of fabrication

Semiconductor material for resistive random access memory

Stacked transistors with contact last

Threshold switching selector based memory

Bottom fin trim isolation aligned with top gate for stacked device architectures

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

Fabrication of non-planar IGZO devices for improved electrostatics

Channel formation for three dimensional transistors

Stacked source-drain-gate connection and process for forming such

DEVICES WITH AIR GAPPING BETWEEN STACKED TRANSISTORS AND PROCESS FOR PROVIDING SUCH

Stacked trigate transistors with dielectric isolation between first and second semiconductor fins

Sidewall interconnect metallization structures for integrated circuit devices