Cedar Park, Texas
United States
33
2020-03-26
The entities that hold a legal rights for patent applications filed by inventor Michael Brad W.:
Brad W. Michael from Cedar Park, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Common high and low random bit error correction logic
#2 | 2019-10-17Common high and low random bit error correction logic
#3 | 2019-08-08Performing error correction in computer memory
#4 | 2019-07-18Tracking address ranges for computer memory errors
#5 | 2018-05-17Arranging binary code based on call graph partitioning
#6 | 2018-03-08Tracking address ranges for computer memory errors
#7 | 2018-03-08Confirming memory marks indicating an error in computer memory
#8 | 2018-03-08Performing error correction in computer memory
#9 | 2018-03-08Managing entries in a mark table of computer memory errors
#10 | 2018-02-22Memory error recovery
#11 | 2017-06-08Arranging binary code based on call graph partitioning
#12 | 2017-05-04Memory error recovery
#13 | 2017-01-12Arranging binary code based on call graph partitioning
#14 | 2016-12-22Synchronization and order detection in a memory system
#15 | 2016-06-30Synchronization and order detection in a memory system
#16 | 2014-09-18Synchronization and order detection in a memory system
#17 | 2012-09-27Multithreaded programmable direct memory access engine
#18 | 2012-08-09Rewriting branch instructions using branch stubs
#19 | 2012-08-02Arranging binary code based on call graph partitioning
#20 | 2012-08-02Dynamically rewriting branch instructions in response to cache line eviction
#21 | 2012-08-02Dynamically rewriting branch instructions to directly target an instruction cache location
#22 | 2012-03-08Arithmetic decoding acceleration
#23 | 2011-12-29Arranging binary code based on call graph partitioning
#24 | 2011-12-29Rewriting branch instructions using branch stubs
#25 | 2011-12-29Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction
#26 | 2011-12-29Dynamically rewriting branch instructions to directly target an instruction cache location
#27 | 2011-03-17Multithreaded programmable direct memory access engine
#28 | 2010-06-24Programmable direct memory access engine
#29 | 2009-03-12Design Structure For A Processor System With Background Error Handling Feature
#30 | 2008-05-01Method and apparatus for testing to determine minimum operating voltages in electronic devices
#31 | 2008-04-17Optimizing a Set of LBIST Patterns to Enhance Delay Fault Coverage
#32 | 2008-04-03Modifying a test pattern to control power supply noise
#33 | 2007-08-09Processor system and methodology with background error handling feature
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