Inventor profile of:

Douglas O. Powell

City:

Endicott, New York

Country:

United States

Published Applications:

25

Last publication date:

2017-05-25

Top Assignees for applications by Douglas O. Powell

The entities that hold a legal rights for patent applications filed by inventor Powell Douglas O.:

Recent patent applications by Powell Douglas O.

Douglas O. Powell from Endicott, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2017-05-25
US20170148749A1
Electricity

Reduced-warpage laminate structure

#2 | 2016-06-02
US20160157357A1
Electricity

Reduced-warpage laminate structure

#3 | 2016-06-02
US20160155708A1
Electricity

Reduced-warpage laminate structure

#4 | 2016-03-17
US20160079117A1
Electricity

Sacrificial carrier dicing of semiconductor wafers

#5 | 2016-03-17
US20160079111A1
Electricity

Sacrificial carrier dicing of semiconductor wafers

#6 | 2014-01-30
US20140033148A1
Physics

Elastic modulus mapping of a chip carrier in a flip chip package

#7 | 2013-03-28
US20130075148A1
Electricity

Reducing impedance discontinuity in packages

#8 | 2012-11-29
US20120299195A1
Electricity

Construction of reliable stacked via in electronic substrates—vertical stiffness control method

#9 | 2012-11-08
US20120279061A1
Electricity

Clustered stacked vias for reliable electronic substrates

#10 | 2012-10-25
US20120267158A1
Electricity

Construction of reliable stacked via in electronic substrates—vertical stiffness control method

#11 | 2010-09-02
US20100218891A1
Electricity

MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYMER DIELECTRIC

#12 | 2009-10-22
US20090265028A1
Electricity

Organic Substrate with Asymmetric Thickness for Warp Mitigation

#13 | 2009-07-30
US20090189290A1
Electricity

Clustered stacked vias for reliable electronic substrates

#14 | 2009-07-30
US20090189289A1
Electricity

EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC SUBSTRATES

#15 | 2009-07-30
US20090188705A1
Electricity

Construction of reliable stacked via in electronic substrates—vertical stiffness control method

#16 | 2009-05-21
US20090126983A1
Electricity

Method and apparatus to reduce impedance discontinuity in packages

#17 | 2008-11-27
US20080290510A1
Electricity

Apparatus for crack prevention in integrated circuit packages

#18 | 2008-09-11
US20080217050A1
Electricity

Multi-layered interconnect structure using liquid crystalline polymer dielectric

#19 | 2008-07-31
US20080178999A1
Electricity

Multi-layered interconnect structure using liquid crystalline polymer dielectric

#20 | 2006-10-31
US10813411
-

Z-interconnections with liquid crystal polymer dielectric films

#21 | 2006-08-01
US10262724
-

Joining member for Z-interconnect in electronic devices without conductive paste

#22 | 2005-08-23
US9665366
-

Organic dielectric electronic interconnect structures and method for making

#23 | 2005-07-14
US20050150686A1
Electricity

Organic dielectric electronic interconnect structures and method for making

#24 | 2005-03-17
US20050057908A1
Electricity

Multi-layered interconnect structure using liquid crystalline polymer dielectric

#25 | 2005-01-13
US20050008833A1
Electricity

Method and structure for small pitch z-axis electrical interconnections

InventorID:

159641 ⎘