Chih Wei Lu

INTERCONNECT STRUCTURE INCLUDING RE-SHAPED CONDUCTIVE INTERCONNECT AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

CONDUCTIVE INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR STRUCTURE INCLUDING ISOLATION ELEMENTS WITH ETCHING-RESISTANT UPPER PORTIONS AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE HAVING AIR GAP STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME

Structure and Method for a Low-K Dielectric With Pillar-Type Air-Gaps

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

INTERCONNECT STRUCTURE WITH REINFORCING SPACER AND METHOD FOR MANUFACTURING THE SAME

INTERCONNECT LAYER AND METHOD FOR MANUFACTURING THE SAME

INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME

SELF-ALIGNED VIA STRUCTURES AND METHODS

SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME

METHODS OF ETCHING METALS IN SEMICONDUCTOR DEVICES

SEMICONDCUTOR DEVICES AND METHODS OF FORMING THE SAME

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

METHOD AND STRUCTURE OF CUT END WITH SELF-ALIGNED DOUBLE PATTERNING

DUAL ETCH-STOP LAYER STRUCTURE

Magnetic tunnel junction devices

SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE

Self-aligned interconnect structure

Integrated chip with inter-wire cavities

Structure and method for a low-k dielectric with pillar-type air-gaps

SELF-ASSEMBLED DIELECTRIC ON METAL RIE LINES TO INCREASE RELIABILITY

Semiconductor arrangement and method of making

INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME

MAGNETO-RESISTIVE RANDOM-ACCESS MEMORY (MRAM) DEVICES WITH SELF-ALIGNED TOP ELECTRODE VIA

SEMICONDUCTOR STRUCTURE

Dielectric on wire structure to increase processing window for overlying via

Interconnect structure having a barrier layer along the sidewall of self-aligned via structures

Structure and formation method of semiconductor device with carbon-containing conductive structure

Semiconductor device

Double patterning approach by direct metal etch

Semiconductor device and a method for fabricating the same

INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAME

Barrier structure on interconnect wire to increase processing window for overlying via

Interconnect conductive structure comprising two conductive materials

Integrated chip with inter-wire cavities

Semiconductor device structure having air gap and method for forming the same

Dual etch-stop layer structure

Self-assembled dielectric on metal RIE lines to increase reliability

Structure and method for an MRAM device with a multi-layer top electrode

Interconnection structure and methods of forming the same

Interconnection structure and methods of forming the same

Self-aligned interconnect structure

Selective deposition of a protective layer to reduce interconnect structure critical dimensions

Dielectric on wire structure to increase processing window for overlying via

Integrated chip with an etch-stop layer forming a cavity

Semiconductor structure and method for forming the same

Integrated circuit

Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability

Method and structure for semiconductor device having gate spacer protection layer

Double patterning approach by direct metal etch

Magnetic tunnel junction devices

Self-aligned cavity strucutre

Method of fabricating self-aligned via structures

Semiconductor arrangement and method of making

Methods of etching metals in semiconductor devices

Method of forming an integrated chip having a cavity between metal features

Self-aligned interconnect structure

Self-aligned cavity strucutre

Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability

Semiconductor arrangement and method of making

Semiconductor device

Magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via

Semiconductor structure and method for forming the same

Selective deposition of a protective layer to reduce interconnect structure critical dimensions

Method and structure of cut end with self-aligned double patterning

Method and structure for semiconductor device having gate spacer protection layer

Methods of etching metals in semiconductor devices

Self-aligned via structures with barrier layers

Method and structure of cut end with self-aligned double patterning

Semiconductor devices and methods of forming the same

Structure and method for a low-K dielectric with pillar-type air-gaps

Semiconductor structure and method for manufacturing the same

Semiconductor device and a method for fabricating the same

Methods of fabricating magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via and structures formed thereby

Integrated circuit

Interconnect structure

Methods of forming interconnect structures using via holes filled with dielectric film

Methods of forming interconnect structures with selectively deposited pillars and structures formed thereby

Memory device

Semiconductor device and method of forming the same

Magnetic tunnel junction devices

Magnetic tunnel junctions

Semiconductor device and method of forming the same

Structure and method for an MRAM device with a multi-layer top electrode

Method for manufacturing memory device

Memory device

Methods of fabricating magneto-resistive random-access memory (MRAM) devices to avoid damaging magnetic tunnel junction (MTJ) structure

Memory device and fabrication method thereof

Structure and method for interconnection

Semiconductor structure and method for manufacturing the same

Vertical MOS transistor

Memory device and fabrication method thereof

Manufacturing techniques and devices for magnetic tunnel junction devices

Method for forming interconnect structure

Magnetic tunnel junctions