Portland, Oregon
United States
40
2026-04-02
The entities that hold a legal rights for patent applications filed by inventor Augustine Charles:
Charles Augustine from Portland, US has applied for patents for these inventions. The list has both pending applications and granted patents:
COMPLEMENTARY FIELD-EFFECT TRANSISTOR STATIC RANDOM-ACCESS MEMORY
#2 | 2026-04-02HIGH PERFORMANCE STATIC RANDOM-ACCESS MEMORY
#3 | 2026-04-02STATIC RANDOM-ACCESS MEMORY WITH PER ROW WRITE-ASSIST
#4 | 2025-09-25BALANCED STATIC RANDOM-ACCESS MEMORY (SRAM)
#5 | 2025-09-25STATIC RANDOM-ACCESS MEMORY
#6 | 2025-02-06RESONATOR AGING TRACKING
#7 | 2024-10-03N-P BALANCED MULTI-PORT REGISTER FILE WITH COMPLEMENTARY FIELD-EFFECT TRANSISTORS (CFETS)
#8 | 2024-05-16THREE-TRANSISTOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY GAIN CELL IN COMPLEMENTARY FIELD EFFECT TRANSISTOR PROCESS
#9 | 2024-02-15MULTI-PORTED REGISTER FILE WITH CFETS
#10 | 2023-09-07SRAM WITH P-TYPE ACCESS TRANSISTORS AND COMPLEMENTARY FIELD-EFFECT TRANSISTOR TECHNOLOGY
#11 | 2022-03-24Unified retention and wake-up clamp apparatus and method
#12 | 2021-08-05All-digital voltage monitor (ADVM) with single-cycle latency
#13 | 2021-08-05Distributed and scalable all-digital low dropout integrated voltage regulator
#14 | 2021-06-24Energy efficient memory array with optimized burst read and write data access
#15 | 2021-04-15Concurrent compute and ECC for in-memory matrix vector operations
#16 | 2021-02-11Techniques for multi-read and multi-write of memory circuit
#17 | 2020-09-22All-digital voltage monitor (ADVM) with single-cycle latency
#18 | 2020-08-13Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation
#19 | 2020-06-11NEAREST NEIGHBOR SEARCH LOGIC CIRCUIT WITH REDUCED LATENCY AND POWER CONSUMPTION
#20 | 2020-04-30NVRAM SYSTEM MEMORY WITH MEMORY SIDE CACHE THAT FAVORS WRITTEN TO ITEMS AND/OR INCLUDES REGIONS WITH CUSTOMIZED TEMPERATURE INDUCED SPEED SETTINGS
#21 | 2020-03-12All-digital closed loop voltage generator
#22 | 2019-12-19HIGH DENSITY NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY
#23 | 2019-08-06Low power retention flip-flop with level-sensitive scan circuitry
#24 | 2019-06-27Techniques for multi-read and multi-write of memory circuit
#25 | 2019-04-18Detecting keywords in audio using a spiking neural network
#26 | 2019-02-07Calibrated biasing of sleep transistor in integrated circuits
#27 | 2019-02-07Apparatus, video processing unit and method for clustering events in a content addressable memory
#28 | 2019-02-07Method and system of temporal-domain feature extraction for automatic speech recognition
#29 | 2018-11-08Post synaptic potential-based learning rule
#30 | 2018-06-28Flip-flop circuit with low-leakage transistors
#31 | 2018-04-19Pre-synaptic learning using delayed causal updates
#32 | 2018-04-19Hybrid compression scheme for efficient storage of synaptic weights in hardware neuromorphic cores
#33 | 2018-03-22Neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a neuromorphic computing environment
#34 | 2017-12-21Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions
#35 | 2017-09-28Technologies for memory management of neural networks with sparse connectivity
#36 | 2017-09-12Physically unclonable function circuit including memory elements
#37 | 2017-08-15Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions
#38 | 2016-10-27Apparatus to reduce retention failure in complementary resistive memory
#39 | 2016-01-14Encryption code generation using spin-torque NANO-oscillators
#40 | 2015-12-31Resistive memory write operation with merged reset
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