Pushkar Ranade

INTEGRATED CIRCUIT STRUCTURES HAVING ULTRA-HIGH CONDUCTIVITY GLOBAL ROUTING

VERTICALLY STACKED MEMORY ARRAYS CORRESPONDING TO RESPECTIVE SINGLE DOPANT TYPES

DEVICE, METHOD AND SYSTEM TO PROVIDE HETEROGENEOUS MEMORY CIRCUIT STACKING

DEVICE, METHOD AND SYSTEM TO PROVIDE ELECTRICAL COUPLING ACROSS ACTIVE LAYERS OF AN INTEGRATED CIRCUIT DIE

DEVICE, METHOD AND SYSTEM TO CONDUCT HEAT THROUGH AN ACTIVE LAYER OF AN INTEGRATED CIRCUIT DIE

INTEGRATED CIRCUIT STRUCTURES HAVING BIT-COST SCALING WITH RELAXED TRANSISTOR AREA

DYNAMIC RANDOM-ACCESS MEMORY USING WIDE BAND GAP MATERIALS

INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL SHARED GATE HIGH-DRIVE THIN FILM TRANSISTORS

TRANSISTOR IN A SILICON CARBIDE LAYER AND A TRANSISTOR IN A GALLIUM NITRIDE LAYER IN A CASCODE DESIGN

TRANSISTOR INCLUDING WIDE BAND GAP MATERIALS

COUPLING A LAYER OF SILICON CARBIDE WITH AN ADJACENT LAYER

MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES

INTEGRATED CIRCUIT STRUCTURES HAVING LOOKUP TABLE DECODERS FOR FPGAS

INTEGRATED CIRCUIT STRUCTURES HAVING ROUTING ACROSS LAYERS OF CHANNEL STRUCTURES

DEVICES IN A SILICON CARBIDE LAYER COUPLED WITH DEVICES IN A GALLIUM NITRIDE LAYER

INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CAPACITORS

INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE POWER DELIVERY AND SIGNAL ROUTING FOR FRONT SIDE DRAM

ULTRA-THIN SEMI-METALS FOR LOW TEMPERATURE CONDUCTION

LOW TEMPERATURE VARACTORS USING VARIABLE CAPACITANCE MATERIALS

FERROELECTRIC TUNNEL JUNCTION DEVICES FOR LOW VOLTAGE AND LOW TEMPERATURE OPERATION

SILICON CARBIDE POWER DEVICES INTEGRATED WITH SILICON LOGIC DEVICES

RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE

SELF-ALIGNMENT LAYER WITH LOW-K MATERIAL PROXIMATE TO VIAS

SOLID STATE ELECTROLYTES FOR BACKEND SUPERCAPACITORS

BURIED VIA THROUGH FRONT-SIDE AND BACK-SIDE METALLIZATION LAYERS WITH OPTIONAL CYLINDRICAL MIM CAPACITOR

LOW TEMPERATURE CAPACITIVELY COUPLED DEVICE FOR LOW NOISE CIRCUITS

TCAM WITH HYSTERETIC OXIDE MEMORY CELLS

VERTICAL PN JUNCTION PHOTONICS MODULATORS WITH BACKSIDE CONTACTS AND LOW TEMPERATURE OPERATION

VERTICAL THROUGH-SILICON WAVEGUIDE FABRICATION METHOD AND TOPOLOGIES

INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY ACCESS TRANSISTOR WITH BACKSIDE CONTACT

INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL TRANSISTOR

INTEGRATED CIRCUIT STRUCTURES HAVING ULTRA-HIGH CONDUCTIVITY GLOBAL ROUTING

INTEGRATED CIRCUIT STRUCTURES HAVING RECESSED CHANNEL TRANSISTOR

INTEGRATED CIRCUIT STRUCTURES HAVING AIRGAPS FOR BACKSIDE SIGNAL ROUTING OR POWER DELIVERY

RECONFIGURABLE VECTOR PROCESSING IN A MEMORY

PERFORMING DISTRIBUTED PROCESSING USING DISTRIBUTED MEMORY

SEPARATELY STORING ENCRYPTION KEYS AND ENCRYPTED DATA IN A HYBRID MEMORY

TRANSISTOR BODY-INDUCED BODY LEAKAGE MITIGATION AT LOW TEMPERATURE

ULTRA-SCALED TRANSISTOR DEVICES TO ENABLE CELL SIZE SCALING

INTEGRATED CIRCUITS WITH NARROW WIDTH INTERCONNECTS AND REDUCED RC DELAY

SCALABLE ARCHITECTURE FOR MULTI-DIE SEMICONDUCTOR PACKAGES

SINGLE CONDUCTIVITY TYPE DEVICES FOR LOW TEMPERATURE COMPUTATION

INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH A METAL CHALCOGENIDE LINER

SRAM CELLS FOR LOW TEMPERATURE INTEGRATED CIRCUIT OPERATION

METHOD AND APPARATUS TO IMPLEMENT AN INTEGRATED CIRCUIT TO OPERATE BASED ON DATA ACCESS CHARACTERISTICS

Providing Orthogonal Subarrays in A Dynamic Random Access Memory

APPARATUS AND METHOD TO IMPLEMENT HOMOMORPHIC ENCYPTION AND COMPUTATION WITH DRAM

PROVIDING FINE GRAIN ACCESS TO PACKAGE MEMORY

METHOD AND APPARATUS TO IMPLEMENT AN INTEGRATED CIRCUIT INCLUDING BOTH DYNAMIC RANDOM-ACCESS MEMORY (DRAM) AND STATIC RANDOM-ACCESS MEMORY (SRAM)

APPARATUS AND METHOD TO IMPLEMENT CACHING AND COMPRESSION IN DRAM FOR CAPACITY IMPROVEMENT

MEMORY STRUCTURE FOR LOW TEMPERATURE OPERATION

SYSTEM DESIGN FOR LOW TEMPERATURE MEMORY

Active regions with compatible dielectric layers

Active regions with compatible dielectric layers

Active regions with compatible dielectric layers

Active regions with compatible dielectric layers