Inventor profile of:

Krishnakanth Sistla

City:

Beaverton, Oregon

Country:

United States

Published Applications:

16

Last publication date:

2021-01-21

Top Assignees for applications by Krishnakanth Sistla

The entities that hold a legal rights for patent applications filed by inventor Sistla Krishnakanth:

Recent patent applications by Sistla Krishnakanth

Krishnakanth Sistla from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2021-01-21
US20210018971A1
Physics

Power control arbitration

#2 | 2019-04-04
US20190102227A1
Physics

THREAD SCHEDULING USING PROCESSING ENGINE INFORMATION

#3 | 2018-12-27
US20180373287A1
Physics

Dynamic maximum frequency limit for processing core groups

#4 | 2018-08-16
US20180232024A1
Physics

Computing system and processor with fast power surge detection and instruction throttle down to provide for low cost power supply unit

#5 | 2014-11-13
US20140337646A1
Physics

Adaptively limiting a maximum operating frequency in a multicore processor

#6 | 2014-06-12
US20140164799A1
Physics

Optimizing power usage by factoring processor architectural events to PMU

#7 | 2014-06-05
US20140157021A1
Physics

Enforcing a power consumption duty cycle in a processor

#8 | 2014-04-03
US20140095905A1
Physics

Computing system and processor with fast power surge detection and instruction throttle down to provide for low cost power supply unit

#9 | 2013-09-26
US20130254572A1
Physics

Optimizing power usage by factoring processor architectural events to PMU

#10 | 2013-09-05
US20130232368A1
Physics

Managing power consumption in a multi-core processor

#11 | 2013-07-11
US20130179716A1
Physics

Dynamically adjusting power of non-core processor circuitry including buffer circuitry

#12 | 2013-06-13
US20130151569A1
Physics

Computing platform interface with memory management

#13 | 2013-03-28
US20130080795A1
Physics

Dynamically adjusting power of non-core processor circuitry including buffer circuitry

#14 | 2012-10-04
US20120254643A1
Physics

Managing power consumption in a multi-core processor

#15 | 2010-06-01
US11526431
-

Adaptively reducing memory latency in a system

#16 | 2009-02-05
US20090037658A1
Physics

Providing an inclusive shared cache among multiple core-cache clusters

InventorID:

170311 ⎘