Folsom, California
United States
61
2025-06-26
The entities that hold a legal rights for patent applications filed by inventor Garg Vivek:
Vivek Garg from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MANAGEMENT OF SUPPLY CURRENT IN SHARED DOMAINS
#2 | 2025-06-19TECHNIQUES FOR MONITORING RESOURCE CIRCUIT HEALTH
#3 | 2025-06-19EFFICIENT ACTIVE IDLE POWER MANAGEMENT FOR COMPUTING SYSTEMS IN AN EFFICIENCY LATENCY CONTROL MODE
#4 | 2025-03-06HIERARCHICAL POWER MANAGEMENT APPARATUS AND METHOD
#5 | 2025-01-02CONFIGURATION OF BASE CLOCK FREQUENCY OF PROCESSOR BASED ON USAGE PARAMETERS
#6 | 2023-10-05Configuration of base clock frequency of processor based on usage parameters
#7 | 2023-07-20SELECTABLE PLATFORM POWER LIMITING TO ENABLE EFFICIENT PERSISTENT MEMORY FLUSH
#8 | 2023-06-22REGISTER INTERFACE FOR COMPUTER PROCESSOR
#9 | 2022-10-27Apparatus and method for processing telemetry data in a virtualized graphics processor
#10 | 2022-04-28Configuration of base clock frequency of processor based on usage parameters
#11 | 2022-03-31Hierarchical power management apparatus and method
#12 | 2021-07-22Apparatus and method for processing telemetry data in a virtualized graphics processor
#13 | 2021-06-24BALANCING POWER BETWEEN DISCRETE COMPONENTS IN A COMPUTE NODE
#14 | 2021-01-21Power control arbitration
#15 | 2020-08-27Thread Scheduling Using Processing Engine Information
#16 | 2020-06-11Apparatus and method for processing telemetry data in a virtualized graphics processor
#17 | 2019-12-19Configuration of base clock frequency of processor based on usage parameters
#18 | 2019-10-17Multicore processor with a control register storing an indicator that two or more cores are to operate at independent performance states
#19 | 2019-06-06Configuring power management functionality in a processor
#20 | 2019-04-04THREAD SCHEDULING USING PROCESSING ENGINE INFORMATION
#21 | 2019-04-04Thread scheduling using processing engine information
#22 | 2019-03-28Techniques to dynamically enable and disable accelerator devices in compute environments
#23 | 2018-11-22APPARATUS AND METHOD FOR THERMAL MANAGEMENT IN A MULTI-CHIP PACKAGE
#24 | 2018-04-05HARDWARE STRESS INDICATORS BASED ON ACCUMULATED STRESS VALUES
#25 | 2017-10-05Systems, methods and devices for using thermal margin of a core in a processor
#26 | 2017-06-22Controlling telemetry data communication in a processor
#27 | 2017-02-02Masking a power state of a core of a processor
#28 | 2016-12-29HARDWARE PROCESSORS AND METHODS TO PERFORM SELF-MONITORING DIAGNOSTICS TO PREDICT AND DETECT FAILURE
#29 | 2016-09-15Dynamically modifying a power/performance tradeoff based on a processor utilization
#30 | 2016-06-16Configuring power management functionality in a processor
#31 | 2016-06-16Configuring power management functionality in a processor
#32 | 2016-05-26Apparatus and method for thermal management in a multi-chip package
#33 | 2016-03-24Configuring power management functionality in a processor
#34 | 2016-01-21Dynamic power limit sharing in a platform
#35 | 2015-02-12Uncore thermal management
#36 | 2014-09-18Processor having frequency of operation information for guaranteed operation under high temperature events
#37 | 2014-07-10Dynamically measuring power consumption in a processor
#38 | 2014-06-19Performing frequency coordination in a multiprocessor system
#39 | 2014-06-05Enforcing a power consumption duty cycle in a processor
#40 | 2014-05-08Method and apparatus for setting an I/O bandwidth-based processor frequency floor
#41 | 2014-04-03Processor having per core and package level P0 determination functionality
#42 | 2014-03-06Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator
#43 | 2014-03-06Configuring power management functionality in a processor
#44 | 2013-12-19Microprocessor-assisted auto-calibration of voltage regulators
#45 | 2013-12-12Dynamic power limit sharing in a platform
#46 | 2013-11-21MASTER SLAVE QPI PROTOCOL FOR COORDINATED IDLE POWER MANAGEMENT IN GLUELESS AND CLUSTERED SYSTEMS
#47 | 2013-09-05Managing power consumption in a multi-core processor
#48 | 2013-07-11Dynamically adjusting power of non-core processor circuitry including buffer circuitry
#49 | 2013-03-28Dynamically adjusting power of non-core processor circuitry including buffer circuitry
#50 | 2012-10-04Managing power consumption in a multi-core processor
#51 | 2012-06-07Dynamically modifying a power/performance tradeoff based on processor utilization
#52 | 2010-11-16Synchronizing control and data paths traversed by a data transaction
#53 | 2010-10-14Uncore thermal management
#54 | 2009-10-06Avoiding deadlocks in a multiprocessor system
#55 | 2009-06-04Store performance in strongly ordered microprocessor architecture
#56 | 2008-04-17Dynamic allocation of home coherency engine tracker resources in link based computing system
#57 | 2008-01-03Uncore thermal management
#58 | 2008-01-03Coordination of snoop responses in a multi-processor system
#59 | 2006-07-11Cache sharing for a chip multiprocessor or multiprocessing system
#60 | 2005-12-13Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
#61 | 2005-10-06Store performance in strongly-ordered microprocessor architecture
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