Inventor profile of:

Navid Azizi

City:

Markham

Country:

Canada

Published Applications:

18

Last publication date:

2019-03-28

Top Assignees for applications by Navid Azizi

The entities that hold a legal rights for patent applications filed by inventor Azizi Navid:

Recent patent applications by Azizi Navid

Navid Azizi from Markham, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-03-28
US20190097636A1
Electricity

Dynamic multicycles for core-periphery timing closure

#2 | 2019-03-05
US13329089
Electricity

Low frequency variation calibration circuitry

#3 | 2017-12-14
US20170359073A1
Electricity

Supporting pseudo open drain input/output standards in a programmable logic device

#4 | 2017-09-21
US20170270995A1
Physics

CIRCUITS AND METHODS FOR DQS AUTOGATING

#5 | 2017-07-04
US13935273
Electricity

Supporting pseudo open drain input/output standards in a programmable logic device

#6 | 2017-06-20
US12803097
Physics

Method and apparatus for performing timing analysis on calibrated paths

#7 | 2016-05-12
US20160133309A1
Physics

Circuits and methods for DQS autogating

#8 | 2015-03-10
US13773468
Physics

Timing analysis with end-of-life pessimism removal

#9 | 2014-11-25
US13715484
Physics

Memory interface circuitry with data strobe signal sharing capabilities

#10 | 2014-09-18
US20140269117A1
Physics

Circuits and methods for DQS autogating

#11 | 2013-10-22
US13149562
-

Methods for calibrating memory interface circuitry

#12 | 2013-05-14
US12137407
-

Pessimism removal in the modeling of simultaneous switching noise

#13 | 2013-03-28
US20130080987A1
Physics

Method and apparatus for simultaneous switching noise optimization

#14 | 2012-10-30
US12557798
-

Reducing simultaneous switching noise in an integrated circuit design during placement

#15 | 2012-10-23
US12833797
-

Method and apparatus for simultaneous switching noise optimization

#16 | 2012-04-03
US12419518
-

Circuit design with incremental simultaneous switching noise analysis

#17 | 2008-07-31
US20080180129A1
Electricity

FPGA ARCHITECTURE WITH THRESHOLD VOLTAGE COMPENSATION AND REDUCED LEAKAGE

#18 | 2005-10-13
US20050226031A1
Physics

Low leakage asymmetric SRAM cell devices

InventorID:

170630 ⎘