Ming WANG

COMBINATION SINGLE-LEVEL CELL PROGRAM MODES TO IMPROVE CELL ENDURANCE

READ RETRY WITH PHYSICAL DEFECT JUDGEMENT

NON-VOLATILE MEMORY WITH LOCATION DEPENDENT CONTROL GATE VOLTAGE

NONVOLATILE MEMORY WITH MULTI-CELL WEIGHT STRUCTURE

IN-PLACE ERASE TECHNIQUES FOR NONVOLATILE MEMORY DEVICES

GATE INDUCED DRAIN LEAKAGE ERASE WITH ADAPTIVE BIAS ON TOP DRAINSIDE SELECT GATE TRANSISTOR AND BOTTOM SOURCE-SIDE SELECT GATE TRANSISTOR

PRE-CHARGE AT READ RECOVERY CLOCK FROM BIT LINE SIDE FOR SUB-BLOCK ONE PERFORMANCE IMPROVEMENT

COMPUTE-IN-MEMORY USING NEURAL NETWORKS STORED IN A NON-VOLATILE MEMORY FOR PREDICTIVE BLOCK HEALTH ASSESSMENT OF THE NON-VOLATILE MEMORY

SUSPEND-RESUME-GO TECHNIQUES FOR MEMORY DEVICES

DEVICE MODE TO IMPROVE DATA RETENTION FOR NAND MLC TECHNOLOGY

NON-VOLATILE MEMORY WITH TAIL BIT IDENTIFICATION FOR IN-PLACE ERROR CORRECTION

NON-VOLATILE MEMORY WITH IN-PLACE ERROR CORRECTION

READ PARAMETER ZONING

SUB-BLOCK MODE BACK PATTERN EFFECT COMPENSATION

STRING BASED ERASE INHIBIT FOR ONE SIDED GATE-INDUCED DRAIN LEAKAGE ERASE

NON-VOLATILE MEMORY WITH IN-PLACE ERROR UPDATING AND CORRECTION

DYNAMIC BIT LINE VOLTAGE DURING PROGRAM VERIFY TO PROVIDE MORE THRESHOLD VOLTAGE BUDGET

ENHANCED BIT ERROR RATE ESTIMATION SCAN PROCESS

APPARATUS AND METHODS FOR READ RETRY WITH CONDITIONAL DATA REFRESH

SMART ERASE INHIBIT

BIT LINE TIMING BASED CELL TRACKING QUICK PASS WRITE FOR PROGRAMMING NON-VOLATILE MEMORY APPARATUSES

NON-VOLATILE MEMORY BITMAP FOR GARBAGE COLLECTION

FIVE LEVEL CELL PROGRAM ALGORITHM WITH APPENDED BIT LEVEL ERASE FOR ADDITIONAL THRESHOLD VOLTAGE BUDGET

SIMULTANEOUS LOWER TAIL VERIFY WITH UPPER TAIL VERIFY

NON-VOLATILE MEMORY WITH CONCURRENT PROGRAMMING

ADAPTIVE ERASE PULSE TO IMPROVE MEMORY CELL ENDURANCE AND ERASE TIME IN NON-VOLATILE MEMORY

CHAIN-LINK CONVERTER

NON-VOLATILE MEMORY WITH DECLINE STATE OPERATION

NON-VOLATILE MEMORY WITH SUB-BLOCK PROGRAMMING

NON-VOLATILE MEMORY WITH SUB-BLOCK ERASE

Non-volatile memory with secure erase

POST-PROGRAM ERASE IN 3D NAND

WATER-BORNE COATING COMPOSITION, ITS PREPARATION METHOD AND APPLICATION THEREOF

BITLINE TIMING-BASED MULTI-STATE PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES

ELECTRICAL SYSTEM AND SUPPORTING DEVICE THEREOF

PROTEIN-DRUG CONJUGATE AND SITE-SPECIFIC CONJUGATING METHOD

SELF-ASSEMBLED AVALANCHE-RESPONSIVE DEVICE AND PREPARATION THEREOF

Non-volatile memory with precise programming

Apparatus and methods for programming memory cells

State look ahead quick pass write algorithm to tighten ongoing natural threshold voltage of upcoming states for program time reduction

Open block boundary group programming for non-volatile memory

Array dependent voltage compensation in a memory device

HIGH-STRENGTH LOW-CARBON MARTENSITIC HIGH HOLE EXPANSION STEEL AND MANUFACTURING METHOD THEREFOR

Copolymer Derived From Substituted Benzopinacol And Use Of The Same As Polymerization Initiator

Non-volatile memory with intentional overprogramming to improve short term data retention issue

BINDING PROTEIN IN FAB-HCAB STRUCTURE

Non-volatile memory with enhanced program operation for last state on slow plane

Non-volatile memory with reverse state program

Foggy-fine programming for memory cells with reduced number of program pulses

Display device and vehicle

Display device and vehicle

Systems and methods for detecting erratic programming in a memory system

Self-adaptive program pulse width for programming 3D NAND memory

COMPLEX-PHASE STEEL HAVING HIGH HOLE EXPANSIBILITY AND MANUFACTURING METHOD THEREFOR

A COATING COMPOSITION, ITS PREPARATION METHOD AND USE THEREOF

Erase technique for checking integrity of non-data word lines in memory device and corresponding firmware

Periodic reduced word line bias which increases channel boosting

Display device and vehicle

Technique to proactively identify potential uncorrectable error correction memory cells and countermeasure in field

Modular multilevel converter system and voltage detection method and open-circuit fault diagnosis method thereof

Smart erase verify test to detect slow-erasing blocks of memory cells

DUAL TARGETING ANTIGEN BINDING MOLECULE

Lymphocyte activation gene-3 (LAG-3) binding antibody and use thereof

LIQUID TEMPERATURE-CONTROL APPARATUS AND METHOD

Modular power supply system

Modular power supply system

Modular power supply system

Modular power supply system

Gate voltage control circuit of insulated gate bipolar transistor and control method thereof

Process for manufacturing apron board of high-speed rail equipment cabin using composite material

Method for molding flame-retardant bending beam integrated with three-dimensional nylon air duct and production mould thereof

Process for manufacturing base board of high-speed rail equipment cabin using composite material

Gate voltage control circuit of insulated gate bipolar transistor and control method thereof

Power unit and power electronic converting device

Semiconductor device, related manufacturing method, and related electronic device

System and method for pulse driving for reducing number of optical fibers

Five-level converting device

Five-level converting device

NLDMOS transistor and fabrication method thereof

Power conversion device and method for transmitting protection signal using the same

Power conversion device, driving device and driving method

Power converter, short-circuit detecting device thereof and short-circuit detecting method thereof

Power conversion system and voltage sampling device thereof

Voltage sampling system

Semiconductor device, related manufacturing method, and related electronic device

FIVE-LEVEL RECTIFIER

Semiconductor devices and fabrication methods thereof

Power semiconductor switch series circuit and control method thereof

Power switch series circuit and control method thereof